An FPGA implementation of the simplex algorithm

Published versio

On the Real-Time Hardware Implementation Feasibility of Joint Radio Resource Management Policies for Heterogeneous Wireless Networks

The study and design of Joint Radio Resource Management (JRRM) techniques is a key and challenging aspect in future heterogeneous wireless systems where different Radio Access Technologies will physically coexist. In these systems, the total available radio resources need to be used in a coordinated way to guarantee adequate satisfaction levels to all users, and maximize the system revenues. In addition to carry out an efficient use of the available radio resources, JRRM algorithms need to exhibit good computational performance to guarantee their future implementation viability. In this context, this paper proposes novel JRRM techniques based on linear programming techniques, and investigates their computational cost when implemented in DSP platforms commonly used in mobile base stations. The obtained results demonstrate the feasibility to implement the proposed JRRM algorithms in future heterogeneous wireless systems

Implementação e ambiente de validação em lógica programável de um decodificador LDPC

A concepção de um circuito integrado envolve uma sequência algorítmica de passos a serem cumpridos para transformar uma ideia em “silício”. De forma simplificada, um desses passos é a implementação de uma determinada lógica usando linguagens apropriadas para esta finalidade. Fundamentalmente é de suma importância efetivar testes e simulações nessa lógica, propiciando ao desenvolvedor menor risco financeiro, pois é uma oportunidade de encontrar defeitos e assim realizar novos e rápidos ciclos de projeto na lógica gerada. Com o intuito de realizar testes que demandariam excessivo tempo computacional de simulação na lógica em questão, é possível realizar a prototipação em lógica programável, em Field Programmable Gate Array (FPGA) e assim, fisicamente exercitar os circuitos digitais nela contida. Porém, para se realizar esta, é necessária a implementação não só do módulo de lógica em questão como também de uma infraestrutura adjacente para estimular o bloco e gerenciar os testes. Neste trabalho é proposta uma arquitetura para executar esses estímulos em um decodificador de correção de erros com estratégia LDPC. Para tal, é efetuada a implementação deste mesmo bloco, que fora anteriormente descrito pelo autor em HDL, juntamente com módulos de gerenciamento dos estímulos para exercitar e coletar os resultados.The conception of an integrated circuit involves an algorithmic sequence of steps to be followed to transform an idea into “silicon”. In a simplified way, one of these steps is the implementation of a certain logic, using languages appropriate for this task. Fundamentally, it is crucial to carry tests and simulations in this logic, providing the developer with less financial risk, as it is an opportunity to find defects and thus carry out new and fast design cycles in the generated logic. To carry out tests that would require excessive computational simulation time in the logic in question, it is possible to perform prototyping in programmable logic, in Field Programmable Gate Array (FPGA), and therefore, physically exercise the digital circuits contained therein. However, to perform, it is necessary to implement the logic module in question and adjacent infrastructure to stimulate the block and manage the tests. An architecture is proposed to execute these stimuli in an error correction decoder with the LDPC strategy in this work. To this end, the implementation of this same block is carried out, which was previously described by the author in HDL, together with modules for managing the stimuli to exercise and collect the results

Custom optimization algorithms for efficient hardware implementation

The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisable hardware code generation tools that generate VHDL code describing custom computing architectures for interior-point methods and a range of first-order constrained optimization methods. Since memory limitations are often important in embedded implementations we develop a custom storage scheme for KKT matrices arising in interior-point methods for control, which reduces memory requirements significantly and prevents I/O bandwidth limitations from affecting the performance in our implementations. To take advantage of the trend towards parallel computing architectures and to exploit the special characteristics of our custom architectures we propose several high-level parallel optimal control schemes that can reduce computation time. A novel optimization formulation was devised for reducing the computational effort in solving certain problems independent of the computing platform used. In order to be able to solve optimization problems in fixed-point arithmetic, which is significantly more resource-efficient than floating-point, tailored linear algebra algorithms were developed for solving the linear systems that form the computational bottleneck in many optimization methods. These methods come with guarantees for reliable operation. We also provide finite-precision error analysis for fixed-point implementations of first-order methods that can be used to minimize the use of resources while meeting accuracy specifications. The suggested techniques are demonstrated on several practical examples, including a hardware-in-the-loop setup for optimization-based control of a large airliner.Open Acces

A dynamically reconfigurable hard-real-time communication protocol for embedded systems

Echtzeitkommunikation ist eine Grundanforderung für viele verteilte eingebettete Systeme. Für eine neue Klasse von Anwendungen sind jedoch nicht nur Echtzeitfähigkeit, sondern auch Flexibilität und Anpassungsfähigkeit notwendige System-Attribute. Um die Flexibilität zu erhöhen, wurde in dieser Arbeit ein neues Kommunikationsprotokoll namens TrailCable konzipiert. Es profitiert von den Eigenschaften des Earliest Deadline First Scheduling-Verfahrens, wie z. B. der optimalen Ausnutzung von Ressourcen und der Unterstützung von heterogenen Tasks. Ein Kommunikationsnetzwerk wird aufgebaut mit Hilfe von voll-Duplex-, Punkt-zu-Punkt-Verbindungen, wobei die Knoten Datenpakete weiterleiten können, um eine Multi-hop Übertragung zu gewährleisten. Es werden Methoden vorgestellt, die es erlauben, automatisch die Kommunikationsanforderungen erfüllende Echtzeit-Kanäle auf das Netzwerk abzubilden. Echtzeit-Kanäle können nur dann aktiviert werden, wenn im Voraus ein Akzeptanztest erfolgreich durchgeführt wurde. Solch eine Prüfung kann mittels eines Tools automatisch erfolgen. Alle dafür notwendigen Netzwerkinformationen werden aus XML-Dateien eingelesen. Zur Laufzeit prüft ein Mechanismus, der Bandbreitenwächter genannt wird, ob die eingelesenen Pakete mit ihrer Spezifikation übereinstimmen, damit Fehler die Echzeitfähigkeit anderer Kanäle nicht beeinträchtigen können. Zeitkritische Funktionen des Kommunikationsprotokolls, wie Scheduling, Bandbreitenwächter, Routing und Uhrsynchronisation, sind mittels dedizierter Hardware implementiert. Ein voll funktionsfähiger FPGA-basierter Prototyp wurde aufgebaut und in zahlreichen Tests evaluiert, um das Echtzeit-Verhalten des Protokolls unter realen Bedingungen zu testen und zu analysieren.Real-time communication is a basic requirement for many distributed embedded systems. However, for an emerging new class of applications not only real-time behavior but also flexibility and adaptability will become necessary system attributes. In order to increase the flexibility of real-time communication systems a new protocol called TrailCable was designed. It takes advantage of the properties of Earliest Deadline First (EDF) scheduling, which include optimal utilization bounds and the possibility to cope with heterogeneous task sets. A communication network is built with full-duplex, point-to-point links, and nodes can route packets to allow multi-hop message delivery. This work introduces methods for automatically mapping real-time channels on a given network directly from communication requirement specifications. The activation of real-time channels in the network is permitted only after a successful schedulability analysis, which can be executed automatically by a tool that checks XML-based network configuration models. At run-time, the characteristics of all incoming packets are checked against their specification by an admission control technique called bandwidth guardian, which is used to ensure that occasional faults will not impair the timeliness of other real-time channels. Time-critical functions of the communication protocol, such as scheduling, admission control, packet routing, and clock synchronization, are implemented by means of dedicated hardware. A fully operational FPGA-based prototype was built and used in different measurement experiments to validate the real-time behavior of the protocol under real conditions.Tag der Verteidigung: 02.04.2012Paderborn, Univ., Diss., 201