Improving reconfigurable systems reliability by combining periodical test and redundancy techniques: a case study

This paper revises and introduces to the field of reconfigurable computer systems, some traditional techniques used in the fields of fault-tolerance and testing of digital circuits. The target area is that of on-board spacecraft electronics, as this class of application is a good candidate for the use of reconfigurable computing technology. Fault tolerant strategies are used in order for the system to adapt itself to the severe conditions found in space. In addition, the paper describes some problems and possible solutions for the use of reconfigurable components, based on programmable logic, in space applications

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller

STR: a student developed star tracker for the ESA-LED ESMO moon mission

In the frame of their engineering degree, ISAE’s students are developing a Star Tracker, with the aim of being the core attitude estimation equipment of the European Moon Student Orbiter. This development goes on since several years and is currently in phase B. We intend to start building an integrated breadboard for the end of the academic year. The STR is composed of several sub-systems: the optical and detection sub-system, the electronics, the mechanics and the software. The optical detection part is based on an in-house developed new generation of APS detectors. The optical train is made of several lenses enclosed in a titanium tube. The electronics includes a FPGA for the pre-processing of the image and a microcontroller in order to manage the high level functions of the instrument. The mechanical part includes the electronics box, as well as the sensor baffle. The design is optimized to minimize the thermo-elastic noise of the assembly. Embedded on ESMO platform, this Star Tracker will be able to compute the satellite‘s attitude, taking into account the specific requirements linked to a Moon mission (illumination, radiation requirements and baffle adaptation to lunar orbit). In order to validate the design, software end-to-end simulation will include a complete simulation of the STR in its lunar dynamic environment. Therefore, we are developing a simple orbital model for the mission (including potential dazzling by celestial bodies)

Neuro-inspired system for real-time vision sensor tilt correction

Neuromorphic engineering tries to mimic biological information processing. Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Currently AER systems are able sense visual and auditory stimulus, to process information, to learn, to control robots, etc. In this paper we present an AER based layer able to correct in real time the tilt of an AER vision sensor, using a high speed algorithmic mapping layer. A codesign platform (the AER-Robot platform), with a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, has been used to implement the system. Testing it with the help of the USBAERmini2 board and the jAER software.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

Computer Architectures to Close the Loop in Real-time Optimization

© 2015 IEEE.Many modern control, automation, signal processing and machine learning applications rely on solving a sequence of optimization problems, which are updated with measurements of a real system that evolves in time. The solutions of each of these optimization problems are then used to make decisions, which may be followed by changing some parameters of the physical system, thereby resulting in a feedback loop between the computing and the physical system. Real-time optimization is not the same as fast optimization, due to the fact that the computation is affected by an uncertain system that evolves in time. The suitability of a design should therefore not be judged from the optimality of a single optimization problem, but based on the evolution of the entire cyber-physical system. The algorithms and hardware used for solving a single optimization problem in the office might therefore be far from ideal when solving a sequence of real-time optimization problems. Instead of there being a single, optimal design, one has to trade-off a number of objectives, including performance, robustness, energy usage, size and cost. We therefore provide here a tutorial introduction to some of the questions and implementation issues that arise in real-time optimization applications. We will concentrate on some of the decisions that have to be made when designing the computing architecture and algorithm and argue that the choice of one informs the other

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them.This work has been partially funded by the Spanish Government under contracts TEC2006-12376 and TEC2009-14446

Embedded microcontroller development for an fpga

En el presente trabajo se describe el proceso de desarrollo inicial de un microcontrolador descripto en VHDL para poder ser implementado sobre una FPGA. Esto comprende la descripción del núcleo del sistema y de sus elementos asociados para formar una unidad de cómputo completa, los bloques que permiten la programación externa y las herramientas necesarias para desarrollar los programas a ejecutar. El objetivo final de este trabajo es no solo obtener la descripción completa del microcontrolador, sino también adquirir experiencia en el campo, para encarar a futuro proyectos de mayor complejidad como sistemas de procesamiento de alta velocidad y procesadores de múltiples núcleos.Fil: Cipollone, Mauro. Universidad Nacional de La Matanza. Departamento de Ingeniería e Investigaciones Tecnológicas. Grupo de Investigación en Lógica Programable; Argentina.Fil: Maidana, Carlos Eduardo. Universidad Nacional de La Matanza. Departamento de Ingeniería e Investigaciones Tecnológicas. Grupo de Investigación en Lógica Programable; Argentina.Fil: Szklanny Fernando Ignacio. Universidad Nacional de La Matanza. Departamento de Ingeniería e Investigaciones Tecnológicas. Grupo de Investigación en Lógica Programable; Argentina