6 research outputs found

    Performance Driven Global Routing Through Gradual Refinement

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    We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method

    An efficient approach to multilayer layer assignment with an application to via minimization

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    An Efficient Multilayer MCM Router Based on Four-Via Routing

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    ... area router, named V4R, for MCM and dense PCB designs. It uses no more than four vias to route every net and yet produces high quality routing solutions. It combines global routing and detailed routing in one step and produces high quality detailed routing solutions directly from the given netlist and module placement. As a result, V4R is independent of net ordering, runs much faster, and uses far less memory compared to other multilayer general area routers. Experimental results show that V4R outperforms both the 3D maze router and the SLICE router significantly

    An efficient multilayer MCM router based on four-via routing

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