A Multi-objective Simulation Based Tool: Application to the Design of High Performance LC-VCOs

Part 16: Optimization Techniques in EnergyInternational audienceThe continuing size reduction of electronic devices imposes design challenges to optimize the performances of modern electronic systems, such as: wireless services, telecom and mobile computing. Fortunately, those design challenges can be overcome thanks to the development of Electronic Design Automation (EDA) tools. In the analog, mixed signal and radio-frequency (AMS/RF) domains, circuit optimization tools have demonstrated their usefulness in addressing design problems taking into account downscaling technological aspects. Recent advances in EDA have shown that the simulation-based sizing technique is a very interesting solution to the ‘complex’ modelling task in the circuit design optimization problem. In this paper we propose a multi-objective simulation-based optimization tool. A CMOS LC-VCO circuit is presented to show the viability of this tool. The tool is used to generate the Pareto front linking two conflicting objectives, namely the VCO Phase Noise and Power Consumption. The accuracy of the results is checked against HSPICE/RF simulations

A collection of fuzzy logic-based tools for the automated design, modelling and test of analog circuits

We have developed a collection of tools for the design, modeling, and test of analog circuits. Sharing a common fuzzy-logic based framework, the tools are part of FASY (Fuzzy-Logic-Based Analog Synthesis), an analog design package developed at the University of Seville. The first tool uses fuzzy logic for topology selection of analog cells. It follows decision rules directly entered by a human expert or automatically generated from its experience with earlier designs. Second, a performance-modeling tool provides a qualitative description of a circuit's behavior. Alternatively, it can use a learning process to accurately model circuit performance. Finally, an analog testing tool uses a fuzzy-neuron classifier to detect and classify faults in analog circuits

A framework for analog circuit optimization

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 49-50).This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design.by Piotr Mitros.M.Eng

Technology Independent Synthesis of CMOS Operational Amplifiers

Analog circuit design does not enjoy as much automation as its digital counterpart. Analog sizing is inherently knowledge intensive and requires accurate modeling of the different parametric effects of the devices. Besides, the set of constraints in a typical analog design problem is large, involving complex tradeoffs. For these reasons, the task of modeling an analog design problem in a form viable for automation is much more tedious than the digital design. Consequently, analog blocks are still handcrafted intuitively and often become a bottleneck in the integrated circuit design, thereby increasing the time to market. In this work, we address the problem of automatically solving an analog circuit design problem. Specifically, we propose methods to automate the transistor-level sizing of OpAmps. Given the specifications and the netlist of the OpAmp, our methodology produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The approach is based on generating an initial first-order design and then refining it. In principle, the refining approach is a simulated-annealing scheme that uses (i) localized simulations and (ii) convex optimization scheme (COS). The optimal set of input variables for localized simulations has been selected by using techniques from Design of Experiments (DOE). To formulate the design problem as a COS problem, we have used monomial circuit models that are fitted from simulation data. These models accurately predict the performance of the circuit in the proximity of the initial guess. The models can also be used to gain valuable insight into the behavior of the circuit and understand the interrelations between the different performance constraints. A software framework that implements this methodology has been coded in SKILL language of Cadence. The methodology can be applied to design different OpAmp topologies across different technologies. In other words, the framework is both technology independent and topology independent. In addition, we develop a scheme to empirically model the small signal parameters like \u27gm\u27 and \u27gds\u27 of CMOS transistors. The monomial device models are reusable for a given technology and can be used to formulate the OpAmp design problem as a COS problem. The efficacy of the framework has been demonstrated by automatically designing different OpAmp topologies across different technologies. We designed a two-stage OpAmp and a telescopic OpAmp in TSMC025 and AMI016 technologies. Our results show significant (10–15%) improvement in the performance of both the OpAmps in both the technologies. While the methodology has shown encouraging results in the sub-micrometer regime, the effectiveness of the tool has to be investigated in the deep-sub-micron technologies

Intelligent electronic design for mechatronic systems

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