13,838 research outputs found

    An analytical model for virtual cut-through routing

    Full text link
    An analytical model of a network with 2-dim torus topology and virtual cut-through routing has been considered in order to find out and analyze certain relationships between network parameters, load and performance. An exact expression for the saturation point (message generation rate at which network saturates) and expressions for the latency as a function of the message generation rate under the assumptions of the “mean field” theory have been obtained. It has been found that the saturation point is inversely proportional to the message length and to the distance between the source and destination. The theoretical results are in a good agreement with small-scale simulation experiments.Accepted manuscrip

    An analytical performance model for the Spidergon NoC

    Get PDF
    Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator

    Requirements for Topology in 3D GIS

    Get PDF
    Topology and its various benefits are well understood within the context of 2D Geographical Information Systems. However, requirements in three-dimensional (3D) applications have yet to be defined, with factors such as lack of users' familiarity with the potential of such systems impeding this process. In this paper, we identify and review a number of requirements for topology in 3D applications. The review utilises existing topological frameworks and data models as a starting point. Three key areas were studied for the purposes of requirements identification, namely existing 2D topological systems, requirements for visualisation in 3D and requirements for 3D analysis supported by topology. This was followed by analysis of application areas such as earth sciences and urban modelling which are traditionally associated with GIS, as well as others including medical, biological and chemical science. Requirements for topological functionality in 3D were then grouped and categorised. The paper concludes by suggesting that these requirements can be used as a basis for the implementation of topology in 3D. It is the aim of this review to serve as a focus for further discussion and identification of additional applications that would benefit from 3D topology. © 2006 The Authors. Journal compilation © 2006 Blackwell Publishing Ltd

    Modeling high-performance wormhole NoCs for critical real-time embedded systems

    Get PDF
    Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.Peer ReviewedPostprint (author's final draft

    Computer interconnection networks with virtual cut-through routing

    Get PDF
    This paper considers a model of a toroidal computer interconnection network with the virtual cut-through routing. The interrelationships between network parameters, load and performance are analyzed. An exact analytical expression for the saturation point and expressions for the latency as a function of the message generation rate under the mean field theory approximation have been obtained. The theoretical results have been corroborated with the results of simulation experiments for various values of network parameters. The network behavior has been found not depending on the torus linear dimensions provided that they are at least twice as large as the message path length. The saturation point has been found to be inversely proportional to the message length in good agreement with the analytical results. A good agreement with Little’s theorem has been found if the network remains in the steady state during the experiment.Accepted manuscrip
    • 

    corecore