12.8 kHz Energy-Efficient Read-Out IC for High Precision Bridge Sensor Sensing System

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 김수환.In the thesis, a high energy-efficient read-out integrated circuit (read-out IC) for a high-precision bridge sensor sensing system is proposed. A low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete-time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC) is implemented. To increase energy-efficiency, CCIA is chosen, which has the highest energy-efficiency among IA types. CCIA has a programmable gain of 1 to 128 that can amplify the small output of the bridge sensor. Impedance boosting loop (IBL) is applied to compensate for the low input impedance, which is a disadvantage of a CCIA. Also, the sensor offset cancellation technique was applied to CCIA to eliminate the offset resulting from the resistance mismatch of the bridge sensor, and the bridge sensor offset from -350 mV to 350 mV can be eliminated. In addition, the output data rate of the read-out IC is designed to be 12.8 kHz to quickly capture data and to reduce the power consumption of the sensor by turning off the sensor and read-out IC for the rest of the time. Generally, bridge sensor system is much slower than 12.8 kHz. To suppress 1/f noise, system level chopping and correlated double sampling (CDS) techniques are used. Implemented in a standard 0.13-μm CMOS process, the ROIC’s effective resolution is 17.0 bits at gain 1 and that of 14.6 bits at gain 128. The analog part draws the average current of 139.4 μA from 3-V supply, and 60.2 μA from a 1.8 V supply.본 논문에서는 고정밀 브리지 센서 센싱 시스템을 위한 에너지 효율이 높은 Read-out Integrated Circuit (read-out IC)를 제안한다. 저 잡음 Capacitively-Coupled Instrumentation Amplifier (CCIA)에 이은 고해상도 Discrete-time Delta-Sigma 변조기(DTΔΣΜ) 아날로그-디지털 변환기(ADC)를 구현하였다. 에너지 효율을 높이기 위해 IA 유형 중 에너지 효율이 가장 높은 CCIA를 선택하였다. CCIA는 브리지 센서의 작은 출력을 증폭할 수 있는 1 에서 128의 프로그래밍 가능한 전압 이득을 가진다. CCIA의 단점인 낮은 입력 임피던스를 보상하기 위해 Impedance Boosting Loop (IBL)을 적용하였다. 또한 CCIA에 센서 오프셋 제거 기술을 적용하여 브리지 센서의 저항 미스매치로 인한 오프셋을 제거 기능을 탑재하였으며 -350mV에서 350mV까지 브리지 센서 오프셋을 제거할 수 있다. Read-out IC의 출력 데이터 전송률은 12.8kHz로 설계하여 데이터를 빠르게 채고 나머지 시간 동안 센서와 read-out IC를 꺼서 센서의 전력 소비를 줄일 수 있도록 설계하였다. 일반적으로 브리지 센서 시스템은 12.8kHz보다 느리기 때문에 이것이 가능하다. 하지만, 일반적인 CCIA는 입력 임피던스 때문에 빠른 속도에서 설계가 불가능하다. 이를 해결하기 위해 demodulate 차핑을 앰프 내부가 아닌 시스템 차핑을 이용해 해결하였다. 1/f 노이즈를 억제하기 위해 시스템 레벨 차핑 및 상관 이중 샘플링(CDS) 기술이 사용되었다. 0.13μm CMOS 공정에서 구현된 read-out IC의 Effective Resolution (ER)은 전압 이득 1에서 17.0비트이고 전압 이득 128에서 14.6비트를 달성하였다. 아날로그 회로는 3 V 전원에서 139.4μA의 평균 전류를, 디지털 회로는 1.8 V 전원에서 60.2μA의 평균 전류를 사용한다.CHAPTER 1 INTRODUCTION 1 1.1 SMART DEVICES 1 1.2 SMART SENSOR SYSTEMS 4 1.3 WHEATSTONE BRIDGE SENSOR 5 1.4 MOTIVATION 8 1.5 PREVIOUS WORKS 10 1.6 INTRODUCTION OF THE PROPOSED SYSTEM 14 1.7 THESIS ORGANIZATION 16 CHAPTER 2 SYSTEM OVERVIEW 17 2.1 SYSTEM ARCHITECTURE 17 CHAPTER 3 IMPLEMENTATION OF THE CCIA 19 3.1 CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER 19 3.2 IMPEDANCE BOOSTING 22 3.3 SENSOR OFFSET CANCELLATION 25 3.4 AMPLIFIER OFFSET CANCELLATION 29 3.5 AMPLIFIER IMPLEMENTATION 32 3.6 IMPLEMENTATION OF THE CCIA 35 CHAPTER 4 INCREMENTAL ΔΣ ADC 37 4.1 INTRODUCTION OF INCREMENTAL ΔΣ ADC 37 4.2 IMPLEMENTATION OF INCREMENTAL ΔΣ MODULATOR 40 CHAPTER 5 SYSTEM-LEVEL DESIGN 43 5.1 DIGITAL FILTER 43 5.2 SYSTEM-LEVEL CHOPPING & TIMING 46 CHAPTER 5 MEASUREMENT RESULTS 48 6.1 MEASUREMENT SUMMARY 48 6.2 LINEARITY & NOISE MEASUREMENT 51 6.3 SENSOR OFFSET CANCELLATION MEASUREMENT 57 6.4 INPUT IMPEDANCE MEASUREMENT 59 6.5 TEMPERATURE VARIATION MEASUREMENT 63 6.6 PERFORMANCE SUMMARY 66 CHAPTER 7 CONCLUSION 68 APPENDIX A. 69 ENERGY-EFFICIENT READ-OUT IC FOR HIGH-PRECISION DC MEASUREMENT SYSTEM WITH IA POWER REDUCTION TECHNIQUE 69 BIBLIOGRAPHY 83 한글초록 87박

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Design of agile signal conditioning circuits for microelectromechanical sensors

Microelectromechanical systems (MEMS) are used in many applications to detect physical parameters and convert them to an electrical signal. The output of MEMS-based transducers is usually not suitable to be directly processed in the digital or the analog domain, and they could be as small as femto farads in capacitive sensing and micro volts in resistive sensing. Consequently, high sensitivity signal conditioning circuits are essential. In this thesis, it is shown that both the noise and input capacitance are important parameters to ensure optimal capacitive sensing. The dominant noise source in MEMS conditioning circuits is flicker noise, and one of the best methods to mitigate flicker noise is the chopping technique. Three different chopping techniques are considered: single chopper amplifier (SCA), dual chopper amplifier (DCA), and two-stage single chopper amplifier (TCA). Also, their sensitivity and power consumption based on the total gain and sensing capacitance are extracted. It is shown that the distribution of gain between the two stages in the DCA and TCA has a significant effect on the sensitivity, and, based on this distribution, the sensitivity and power consumption change significantly. For small sensor capacitances, the highest sensitivity could be achieved by a DCA because of its ability to decrease the noise floor and the input sensor capacitance simultaneously. A novel DCA is proposed to reach higher sensitivity and reduced power consumption. In this DCA, two supply voltages are utilized, and the second stage is composed of two parallel paths that improve the SNR and provide two gain settings. This circuit is fabricated in the GlobalFoundries 0.13 μm CMOS technology. The measurement results show a power consumption of 2.66 μW for the supply voltage of 0.7 V and of 3.26 μW for the supply voltage of 1.2 V. The single path DCA has a gain of 34 dB with bandwidth of 4 kHz and input noise floor of 25 nV/√Hz. The dual path DCA has a gain of 38 dB with bandwidth of 3 kHz and input noise floor of 40 nV/√Hz. To be able to detect the signal near DC frequencies, another circuit is proposed which has a configurable bandwidth and a sub-μHz noise corner frequency. This circuit is composed of three stages, and three chopping frequencies are used to mitigate the flicker noise of the three stages. The simulated circuit is designed in the GlobalFoundries 0.13 μm CMOS technology with supply voltages of 0.4 V and 1.2 V. The total power consumption is of 6.7 μW. A gain of 68 dB and bandwidths of 1, 10, 100 and 1000 Hz are achieved. The input referred noise floor is of 20.5 nV/√Hz and the design attains a good power efficiency factor of 4.0. In the capacitive mode, the noise floor is of 3.6 zF for a 100 fF capacitance sensor