A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC

The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irradiation. Various gain selection algorithms to achieve the extended dynamic range are implemented and tested.Comment: 22 pages, 22 figures, accepted by JINS

Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

IUS/payload communication system simulator configuration definition study

The requirements and specifications for a general purpose payload communications system simulator to be used to emulate those communications system portions of NASA and DOD payloads/spacecraft that will in the future be carried into earth orbit by the shuttle are discussed. For the purpose of on-orbit checkout, the shuttle is required to communicate with the payloads while they are physically located within the shuttle bay (attached) and within a range of 20 miles from the shuttle after they have been deployed (detached). Many of the payloads are also under development (and many have yet to be defined), actual payload communication hardware will not be available within the time frame during which the avionic hardware tests will be conducted. Thus, a flexible payload communication system simulator is required

The 727 approach energy management system avionics specification (preliminary)

Hardware and software requirements for an Approach Energy Management System (AEMS) consisting of an airborne digital computer and cockpit displays are presented. The displays provide the pilot with a visual indication of when to manually operate the gear, flaps, and throttles during a delayed flap approach so as to reduce approach time, fuel consumption, and community noise. The AEMS is an independent system that does not interact with other navigation or control systems, and is compatible with manually flown or autopilot coupled approaches. Operational use of the AEMS requires a DME ground station colocated with the flight path reference

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Low-cost, high-precision DAC design based on ordered element matching and verification against undesired operating points for analog circuits

Over the past 50 years, the integrated circuit (IC) industry has grown rapidly, following the famous ``Moore\u27s law. The process feature size keeps shrinking, whereby the performance of digital circuits is constantly enhanced and their cost constantly decreases. However, with the system integration and the development of system on chip (SoC), nearly all of today\u27s ICs contain analog/mixed-Signal circuits. Although a mixed-signal SoC is primarily digital, the analog circuit design and verification consume most of the resources, and the dominant source of IC breakdowns is attributable to the analog circuits. One important reason for the high cost and risk of breakdowns of analog circuits is that the technology advancement does not benefit many analog and mixed-signal circuits, and in fact imposes higher requirements on their performance. With process scaling, many important parameters of integrated circuit components degrade, which cause a drop in many key aspects of performance of analog circuits. Many analog circuits rely on matched circuit components (transistors, resistors, or capacitors) to achieve the required linearity performance; examples are amplifiers, digital-to-analog converters (DACs), etc. However, shrinking of the feature sizes increases the circuit components mismatch, thereby making it more difficult to maintain circuit accuracy. Therefore, to reduce the cost of analog circuit design, designers should propose new structures whose key performance can be improved by the technology scaling. In this dissertation, we propose a low-cost, high-precision DAC structure based on ordered element matching (OEM) theory. High matching accuracy can be achieved by applying OEM calibration to the resistors in unary weighted segments and calibrating the gain error between different segments by calibration DAC (CalDAC). As a design example to verify the proposed structure, a high-precision DAC is designed in a 130 nm Global Foundry (GF) CMOS process. The 130 nm GF process features high-density digital circuits and is a typical process which is constantly enhanced by the scaling of device dimensions and voltage supply; implementation of a high-precision DAC in such process is important to decreasing the costs of high-precision DAC designs. As a result, our proposed DAC structure is demonstrated to be able to significantly lower the cost of high-precision DAC design. Another reason for the high cost and risk of breakdowns of analog circuits arises from the complexity of analog circuit working states. Most digital circuits serve as logic functions, so that digital transistors work in only two states, either low or high. In contrast, analog circuits have much more complicated functions; they may work in multiple operating points, since various feedback approaches are applied in analog circuits to enhance their performance. Circuits with undetected operating points can be devastating, particularly when they are employed in critical applications such as automotive, health care, and military products. However, since the existing circuit simulators provide only a single operating point, recognizing the existence of undesired operating points depends largely on the experiences of designers. In some circuits, even the most experienced designers may not be aware that a circuit they designed has undesired operating points, which often go undetected in the standard simulations in the design process. To identify undesired operating points in an analog circuit and reduce its risk of breakdowns, a systematic verification method against undesired operating points in analog circuits is proposed in this dissertation. Unlike traditional methods of finding all operating points, this method targets only searches for voltage intervals containing undesired operating points. To achieve this, our method first converts the circuit into a corresponding graph and locates the break point to break all the positive feedback loops (PFLs). For one dimensional verification, divide and contraction algorithms could be applied to identify undesired operating points. Two dimensional vector field methods are used to solve the two dimensional verifications. Based on the proposed verification methods against undesired operating points, an EDA tool called ``ITV is developed to identify undesired operating points in analog and mixed-signal circuits. Simulation results show ITV to be effective and efficient in identifying undesired operating points in a class of commonly used benchmark circuits that includes bias generators, voltage references, temperature sensors, and op-amp circuits

Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered