Homeostatic Fault Tolerance in Spiking Neural Networks : A Dynamic Hardware Perspective

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior

Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation

A novel approach to hardware fault tolerance is demonstrated that takes inspiration from the human immune system as a method of fault detection. The human immune system is a remarkable system of interacting cells and organs that protect the body from invasion and maintains reliable operation even in the presence of invading bacteria or viruses. This paper seeks to address the field of electronic hardware fault tolerance from an immunological perspective with the aim of showing how novel methods based upon the operation of the immune system can both complement and create new approaches to the development of fault detection mechanisms for reliable hardware systems. In particular, it is shown that by use of partial matching, as prevalent in biological systems, high fault coverage can be achieved with the added advantage of reducing memory requirements. The development of a generic finite-state-machine immunization procedure is discussed that allows any system that can be represented in such a manner to be "immunized" against the occurrence of faulty operation. This is demonstrated by the creation of an immunized decade counter that can detect the presence of faults in real tim

End-to-End Direct Digital Synthesis Simulation and Mathematical Model to Minimize Quantization Effects of Digital Signal Generation

Direct digital synthesis (DDS) architectures are becoming more prevalent as modern digital-to-analog converter (DAC) and programmable logic devices evolve to support higher bandwidths. The DDS architecture provides the benefit of digital control but at a cost of generating spurious content in the spectrum. The generated spurious content may cause intermodulation distortion preventing proper demodulation of the received signal. The distortion may also interfere with the neighboring frequency bands. This article presents the various DDS architectures and explores the DDS architecture which provides the most digital reconfigurability with the lowest spurious content. End-to-end analytical equations, numerical and mathematical models are developed to determine the location and power levels of spurs. Afterwards, the analytical equations, numerical and mathematical models are shown to be consistent with the experimental data. A developer can use the information to design a DDS architecture that meets their minimum requirements

The Murchison Widefield Array: Design Overview

The Murchison Widefield Array (MWA) is a dipole-based aperture array synthesis telescope designed to operate in the 80-300 MHz frequency range. It is capable of a wide range of science investigations, but is initially focused on three key science projects. These are detection and characterization of 3-dimensional brightness temperature fluctuations in the 21cm line of neutral hydrogen during the Epoch of Reionization (EoR) at redshifts from 6 to 10, solar imaging and remote sensing of the inner heliosphere via propagation effects on signals from distant background sources,and high-sensitivity exploration of the variable radio sky. The array design features 8192 dual-polarization broad-band active dipoles, arranged into 512 tiles comprising 16 dipoles each. The tiles are quasi-randomly distributed over an aperture 1.5km in diameter, with a small number of outliers extending to 3km. All tile-tile baselines are correlated in custom FPGA-based hardware, yielding a Nyquist-sampled instantaneous monochromatic uv coverage and unprecedented point spread function (PSF) quality. The correlated data are calibrated in real time using novel position-dependent self-calibration algorithms. The array is located in the Murchison region of outback Western Australia. This region is characterized by extremely low population density and a superbly radio-quiet environment,allowing full exploitation of the instrumental capabilities.Comment: 9 pages, 5 figures, 1 table. Accepted for publication in Proceedings of the IEE

Implementation of JPEG compression and motion estimation on FPGA hardware

A hardware implementation of JPEG allows for real-time compression in data intensivve applications, such as high speed scanning, medical imaging and satellite image transmission. Implementation options include dedicated DSP or media processors, FPGA boards, and ASICs. Factors that affect the choice of platform selection involve cost, speed, memory, size, power consumption, and case of reconfiguration. The proposed hardware solution is based on a Very high speed integrated circuit Hardware Description Language (VHDL) implememtation of the codec with prefered realization using an FPGA board due to speed, cost and flexibility factors; The VHDL language is commonly used to model hardware impletations from a top down perspective. The VHDL code may be simulated to correct mistakes and subsequently synthesized into hardware using a synthesis tool, such as the xilinx ise suite. The same VHDL code may be synthesized into a number of sifferent hardware architetcures based on constraints given. For example speed was the major constraint when synthesizing the pipeline of jpeg encoding and decoding, while chip area and power consumption were primary constraints when synthesizing the on-die memory because of large area. Thus, there is a trade off between area and speed in logic synthesis