Lityum iyon piller için NMC/Karbon hibrit kompozitlerin sentezi ve elektrokimyasal karakterizasyonu

06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Anahtar kelimeler: Li-İyon Pil, Li-NMC, Grafen, Karbon Nanotüp, Sol jel Geçen zaman içinde teknolojinin hızla gelişiyor olması buna bağlı olarak bireysel beklentilerin ve taleplerin artmasına sebep olmuştur. Gelişen teknoloji ile beraber rekabetin artması ile hammadde ve enerji kaynaklarının tükenme riski ve çevresel problemler her geçen gün artmaktadır. Tüm bu sebeplerden dolayı enerji depolama konusundaki çalışmalar hız kazanmıştır. Enerji depolamak için çeşitli teknolojiler düşünüldüğünde, lityum iyon piller özellikle elektrikli ve hibrid araçlar için artarak devam eden taleplere en umut verici seçeneklerden biridir. Enerji depolamada ana sınırlayıcı faktör Li-iyon pildeki katot materyalinin performansıdır. Mevcut pazardaki katot malzemelerine alternatif olarak iyi pil performansı, yapısal stabilite, düşük maliyet ve fiyat, düşük toksisite gibi özelliklere sahip olan Li-NMC katot materyali geliştirilmiştir. Bu yüksek lisans tez çalışmasında, Li-NMC'nin hem elektrokimyasal hem de yapısal özellikleri garfen, karbon nanotüp ve garfen/karbon nanotüp takviyesi yapılarak geliştirilmiştir. Bu amaç doğrultusunda sol-jel yöntemi kullanılarak mikron altı boyutta Li-NMC üretilmiştir. Takviye malzemeleri olarak Hummers metodu ile üretilmiş grafen ve aktive edilmiş karbon nanotüp kullanılmıştır. Üretilen materyallerin karakterizasyonu için X- ışını difraksiyonu (XRD), alan emisyonlu taramalı elektron mikroskobu (FE-SEM), elementel dağılım spektroskopisi (EDS) ve noktasal haritalama analizlari kulanılmıştır. Elektrokimyasal analizlerde empedans spektroskoisi (EIS), çevrimsel voltametri (CV) ve galvanostatik şarj/deşarj testleri yapılmıştır. Elektrokimyasal testler sonrasında elde edilen sonuçlarda Li-NMC/Grafen/KNT serbest elektrotun ticari olarak kullanılmakta olan Li-NMC'ye göre daha üstün elektrokimyasal performans sergilediği gözlemlenmiştir.Keywords: Li-Ion Battery, Li-NMC, Graphene, Carbon Nanotube, Sol-gel The rapid development of technology over time has led to an increase in individual expectations and demands. Increasing competition with the developing technology, the risks of exhaustion of raw materials and energy resources and environmental problems are increasing day by day. For all these reasons, the work on energy storage has gained more interest. When considering various technologies for storing energy, lithium ion batteries are one of the most promising options, especially for demanding electric and hybrid vehicles. The main limiting factor in energy storage is the performance of cathode material in the Li-ion batteries. Li-NMC cathode material with good battery performance, structural stability, low cost and price, low toxicity has been considered as an alternative to existing cathode electrodes. In this master thesis study, both electrochemical and structural properties of Li-NMC were improved by graphene, carbon nanotube and graphene/carbon nanotube reinforcement. In order to achieve this purpose, sub-micron Li-NMC were produced by sol-gel method. Graphene produced by Hummers method and activated carbon nanotubes were used as reinforcement elements. The as-synthesized materials were then characterized by the X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), elemental dot-map spectroscopy (EDS). Electrochemical analyzes were performed with impedance spectroscopy (EIS), cyclic voltammetry (CV) and galvanostatic charge/discharge tests. It has been observed that Li-NMC/Graphene/MWCNNT free standing electrode exhibits superior electrochemical performance when compared with commercially available Li-NMC after electrochemical tests

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system