3,037 research outputs found
Modeling of CMOS devices and circuits on flexible ultrathin chips
The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-Ī¼m technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 Ī¼m using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)
A Nanoscale Parametric Feedback Oscillator
We describe and demonstrate a new oscillator topology, the parametric feedback oscillator (PFO). The PFO paradigm is applicable to a wide variety of nanoscale devices and opens the possibility of new classes of oscillators employing innovative frequency-determining elements, such as nanoelectromechanical systems (NEMS), facilitating integration with circuitry and system-size reduction. We show that the PFO topology can also improve nanoscale oscillator performance by circumventing detrimental effects that are otherwise imposed by the strong device nonlinearity in this size regime
Correlation between the golden ratio and nanowire transistor performance
An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect to the 5-nm complementary metal-oxide-semiconductor (CMOS) application. The results reveal that the amount of mobile charge in the channel and intrinsic speed of the device are determined by the device geometry and could also be correlated to the golden ratio (Phi). This paper highlights the issue that the optimization of NWT geometry could reduce the impact of the main sources of statistical variability on the Figure of Merit (FoM) of devices. In the context of industrial early successes in fabricating vertically stacked NWT, ensemble Monte Carlo (MC) simulations with quantum correction are used to accurately predict the drive current. This occurs alongside a consideration of the degree to which the carrier transport in the vertically stacked lateral NWTs are complex
Device modelling for bendable piezoelectric FET-based touch sensing system
Flexible electronics is rapidly evolving towards
devices and circuits to enable numerous new applications. The
high-performance, in terms of response speed, uniformity and
reliability, remains a sticking point. The potential solutions for
high-performance related challenges bring us back to the timetested
silicon based electronics. However, the changes in the
response of silicon based devices due to bending related stresses is
a concern, especially because there are no suitable models to
predict this behavior. This also makes the circuit design a
difficult task. This paper reports advances in this direction,
through our research on bendable Piezoelectric Oxide
Semiconductor Field Effect Transistor (POSFET) based touch
sensors. The analytical model of POSFET, complimented with
Verilog-A model, is presented to describe the device behavior
under normal force in planar and stressed conditions. Further,
dynamic readout circuit compensation of POSFET devices have
been analyzed and compared with similar arrangement to reduce
the piezoresistive effect under tensile and compressive stresses.
This approach introduces a first step towards the systematic
modeling of stress induced changes in device response. This
systematic study will help realize high-performance bendable
microsystems with integrated sensors and readout circuitry on
ultra-thin chips (UTCs) needed in various applications, in
particular, the electronic skin (e-skin)
Ultra-Stretchable Interconnects for High-Density Stretchable Electronics
The exciting field of stretchable electronics (SE) promises numerous novel
applications, particularly in-body and medical diagnostics devices. However,
future advanced SE miniature devices will require high-density, extremely
stretchable interconnects with micron-scale footprints, which calls for proven
standardized (complementary metal-oxide semiconductor (CMOS)-type) process
recipes using bulk integrated circuit (IC) microfabrication tools and
fine-pitch photolithography patterning. Here, we address this combined
challenge of microfabrication with extreme stretchability for high-density SE
devices by introducing CMOS-enabled, free-standing, miniaturized interconnect
structures that fully exploit their 3D kinematic freedom through an interplay
of buckling, torsion, and bending to maximize stretchability. Integration with
standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid
(F2R) post-processing technology to make the back-end-of-line interconnect
structures free-standing, thus enabling the routine microfabrication of
highly-stretchable interconnects. The performance and reproducibility of these
free-standing structures is promising: an elastic stretch beyond 2000% and
ultimate (plastic) stretch beyond 3000%, with 10
million cycles at 1000% stretch with <1% resistance change. This generic
technology provides a new route to exciting highly-stretchable miniature
devices.Comment: 13 pages, 5 figure, journal publicatio
Microelectronic engineering education for emerging frontiers
With the support provided by the National Science Foundation and RIT Provostās vision for providing flexible curricula, the department of Microelectronic Engineering has instituted new and enhanced program initiatives ā (1) offering a semiconductor processing minor for other science and engineering programs promoting access to state-of-the art semiconductor fabrication facilities to students from other programs; (2) crafting a five course elective sequence within the existing curriculum by eliminating legacy material and course consolidation; (3) developing a concentration program in nanotechnology and MEMS; (4) outreach programs for targeting larger and diverse participation in preparing workforce for the nationās future high tech industry; (5) enhance student learning through co-op and service. The mission is to generate multi faceted work force for the future semiconductor technologies and emerging frontiers spinning off from microelectronics, while simultaneously promoting enrollment particularly from women and minority students
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