Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Caracterización y medida de consumo de energía en sistemas basados en FPGAs de XILINX

En este trabajo de fin de máster se ha estudiado el consumo de potencia de circuitos digitales para la placa BASYS2 y la eficacia y precisión de la herramienta de estimación de consumo Xpower Analyzer de XILINX. Los resultados de la estimación del consumo de potencia de circuitos digitales es contrastada con medidas físicas realizadas en laboratorio, dicha estimación de consumo de energía como ya dijimos se realiza con la herramienta XPA ISE14.7 de XILINX. El objetivo principal del proyecto es analizar un circuito digital determinado variando la longitud de los vectores de entrada y salida del mismo, estudiando a la par también los parámetros más importantes a la hora de reducir el consumo de energía de estos sistemas digitales basados en FPGAs. Son cuatro los términos matemáticos involucrados en la medida del consumo de potencia en circuitos digitales, pero el más importante a la hora de reducir el consumo es el de la potencia dinámica, que es la potencia relacionada a las conmutaciones en los nodos del circuito, tanto internamente como en las entradas y salidas. Para la medida física del consumo de potencia en la placa BASYS2, existe una variedad de sistemas de adquisición de datos en este proyecto optamos por el más sencillo de todos, el cual no añadía consumo de más que el que solo queríamos medir que es el de la placa en cuestión, este sistema consiste en una resistencia de Shunt en serie con la fuente y la placa BASYS2, lo que medimos es la tensión e indirectamente con el valor de la resistencia calculamos la intensidad, teniendo estos datos calculamos fácilmente el consumo de potencia. Para el estudio contamos también con un generador de números aleatorios LFSR, el cual también se detalla en los anexos de este libro específicamente el Apéndice A, se ha utilizado solo un bloque generador de números aleatorios para cada experimento con el circuito, a este código Generador de números aleatorios integramos un multiplicador genérico cuyo código esta también detallado en el Apéndice B, a la hora de variar las entradas y salidas y obtener así una medida de la lógica en el sistema. En la placa BASYS2 realizamos varias pruebas, con el circuito multiplicador genérico, variamos las entradas salidas del mismo de la siguiente forma, para una entrada de 2 bits, la salida correspondiente es de 4 bits, para una entrada de 3 bits la salida correspondiente seria de 6 bits, y asi sucesivamente hasta probar entradas de N bits con salida de 2*Nbits. Como comentamos al principio hemos utilizado las herramientas del ISE14.7 como ISIM para realizar las simulaciones, y la herramienta XPower Analyzer para estimar la energía consumida por los nodos de cada prueba. Se han realizado en total 44 diferentes pruebas sobre la BASYS2, y un total de 44 simulaciones, y estimaciones de potencia con el XPower Analyzer de XILINX, utilizamos los circuitos internos de gestión de reloj llamados DCM del inglés Digital Clock managers, cabe mencionar que si generamos una frecuencia menor a 50MHz(frecuencia de trabajo por defecto de la BASYS2) con el DCM la potencia no será menor por ser la frecuencia menor precisamente si no que aumentara el consumo debido a la utilización de estos bloques DCM, utilizamos también estos bloques para realizar las pruebas a reloj parado que se detallan en el capítulo de metodología de este libro. La conclusión a la que llegamos y que se puede ver a través de las pruebas realizadas es que al aumentar la longitud de los vectores de entrada/salida del circuito aumenta la potencia consumida, ya que se utilizan más recursos de la placa, lo que es muy intuitivo, y nos lleva a concluir que el efecto de añadir más lógica a un sistema aumenta el consumo de potencia. Lo anterior implica que a la hora de reducir el consumo de potencia de un sistema, es necesario reducir al máximo la lógica del mismo, que es una técnica de bajo consumo para circuitos digitales tenida en cuenta por los programadores

Address Bus Encoding Techniques for System-Level Power Optimization

The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I#O interfaces can provide signi#cant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated byareal microprocessor, have demonstrated the e#ectiveness of the proposed methods

Address Bus Encoding Techniques for System-Level Power Optimization

reserved5The Design Automation and Test in Europe, DATE, is Europe’s leading international electronic systems design conference for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. It combines the conference with Europe’s leading international exhibition for electronic design, automation and test. To celebrate the tenth anniversary of DATE, the Editors have compiled this book with the aim to highlight some of the most influential technical contributions from ten years of DATE. Selecting 30 papers, only 3 papers from each year, is a challenging endeavor. Although the impact of papers from the first years of DATE can be determined through various citation indexes, the impact from the later years still have to be seen. Together with all 10 Program Chairs, the Editors have made a selection of the most influential papers covering the very broad range of topics which is characteristic for DATE. The present chapter discusses how the power dissipated by system-level buses is the largest contributionbto the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overallbpower budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.L. Benini; G. De Micheli; E. Macii; D. Sciuto; C. SilvanoL., Benini; G., De Micheli; E., Macii; Sciuto, Donatella; Silvano, Cristin

Address Bus Encoding Techniques for System-Level Power Optimization

The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I#O interfaces can provide signi#cant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated byareal microprocessor, have demonstrated the e#ectiveness of the proposed methods.

Multilayer Modeling and Design of Energy Managed Microsystems

Aggressive energy reduction is one of the key technological challenges that all segments of the semiconductor industry have encountered in the past few years. In addition, the notion of environmental awareness and designing “green” products is yet another major driver for ultra low energy design of electronic systems. Energy management is one of the unique solutions that can address the simultaneous requirements of high-performance, (ultra) low energy and greenness in many classes of computing systems; including high-performance, embedded and wireless. These considerations motivate the focus of this dissertation on the energy efficiency improvement of Energy Managed Microsystems (EMM or EM2). The aim is to maximize the energy efficiency and/or the operational lifetime of these systems. In this thesis we propose solutions that are applicable to many classes of computing systems including high-performance and mobile computing systems. These solutions contribute to make such technologies “greener”. The proposed solutions are multilayer, since they belong to, and may be applicable to, multiple design abstraction layers. The proposed solutions are orthogonal to each other, and if deployed simultaneously in a vertical system integration approach, when possible, the net benefit may be as large as the multiplication of the individual benefits. At high-level, this thesis initially focuses on the modeling and design of interconnections for EM2. For this purpose, a design flow has been proposed for interconnections in EM2. This flow allows designing interconnects with minimum energy requirements that meet all the considered performance objectives, in all specified system operating states. Later, models for energy performance estimation of EM2 are proposed. By energy performance, we refer to the improvements of energy savings of the computing platforms, obtained when some enhancements are applied to those platforms. These models are based on the components of the application profile. The adopted method is inspired by Amdahl’s law, which is driven by the fact that ‘energy’ is ‘additive’, as ‘time’ is ‘additive’. These models can be used for the design space exploration of EM2. The proposed models are high-level and therefore they are easy to use and show fair accuracy, 9.1% error on average, when compared to the results of the implemented benchmarks. Finally, models to estimate energy consumption of EM2 according to their “activity” are proposed. By “activity” we mean the rate at which EM2 perform a set of predefined application functions. Good estimations of energy requirements are very useful when designing and managing the EM2 activity, in order to extend their battery lifetime. The study of the proposed models on some Wireless Sensor Network (WSN) application benchmark confirms a fair accuracy for the energy estimation models, 3% error on average on the considered benchmarks

System-level power optimization:techniques and tools

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software