89,720 research outputs found

    An Adaptive Design Methodology for Reduction of Product Development Risk

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    Embedded systems interaction with environment inherently complicates understanding of requirements and their correct implementation. However, product uncertainty is highest during early stages of development. Design verification is an essential step in the development of any system, especially for Embedded System. This paper introduces a novel adaptive design methodology, which incorporates step-wise prototyping and verification. With each adaptive step product-realization level is enhanced while decreasing the level of product uncertainty, thereby reducing the overall costs. The back-bone of this frame-work is the development of Domain Specific Operational (DOP) Model and the associated Verification Instrumentation for Test and Evaluation, developed based on the DOP model. Together they generate functionally valid test-sequence for carrying out prototype evaluation. With the help of a case study 'Multimode Detection Subsystem' the application of this method is sketched. The design methodologies can be compared by defining and computing a generic performance criterion like Average design-cycle Risk. For the case study, by computing Average design-cycle Risk, it is shown that the adaptive method reduces the product development risk for a small increase in the total design cycle time.Comment: 21 pages, 9 figure

    Simulation of learning in supply partnerships

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    This paper introduces a general, formal treatment of dynamic constraints, i.e., constraints on the state changes that are allowed in a given state space. Such dynamic constraints can be seen as representations of "real world" constraints in a managerial context. The notions of transition, reversible and irreversible transition, and transition relation will be introduced. The link with Kripke models (for modal logics) is also made explicit. Several (subtle) examples of dynamic constraints will be given. Some important classes of dynamic constraints in a database context will be identified, e.g. various forms of cumulativity, non-decreasing values, constraints on initial and final values, life cycles, changing life cycles, and transition and constant dependencies. Several properties of these dependencies will be treated. For instance, it turns out that functional dependencies can be considered as "degenerated" transition dependencies. Also, the distinction between primary keys and alternate keys is reexamined, from a dynamic point of view.

    Quick Search for Rare Events

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    Rare events can potentially occur in many applications. When manifested as opportunities to be exploited, risks to be ameliorated, or certain features to be extracted, such events become of paramount significance. Due to their sporadic nature, the information-bearing signals associated with rare events often lie in a large set of irrelevant signals and are not easily accessible. This paper provides a statistical framework for detecting such events so that an optimal balance between detection reliability and agility, as two opposing performance measures, is established. The core component of this framework is a sampling procedure that adaptively and quickly focuses the information-gathering resources on the segments of the dataset that bear the information pertinent to the rare events. Particular focus is placed on Gaussian signals with the aim of detecting signals with rare mean and variance values

    Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

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    Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
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