4 research outputs found
Can deep-sub-micron device noise be used as the basis for probabilistic neural computation?
This thesis explores the potential of probabilistic neural architectures for computation with future
nanoscale Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). In particular,
the performance of a Continuous Restricted Boltzmann Machine {CRBM) implemented
with generated noise of Random Telegraph Signal (RTS) and 1/ f form has been studied with
reference to the 'typical' Gaussian implementation. In this study, a time domain RTS based
noise analysis capability has been developed based upon future nanoscale MOSFETs, to represent
the effect of nanoscale MOSFET noise on circuit implementation in particular the
synaptic analogue multiplier which is subsequently used to implement stochastic behaviour
of the CRBM. The result of this thesis indicates little degradation in performance from that
of the typical Gaussian CRBM. Through simulation experiments, the CRBM with nanoscale
MOSFET noise shows the ability to reconstruct training data, although it takes longer to converge
to equilibrium. The results in this thesis do not prove that nanoscale MOSFET noise
can be exploited in all contexts and with all data, for probabilistic computation. However,
the result indicates, for the first time, that nanoscale MOSFET noise has the potential to be
used for probabilistic neural computation hardware implementation. This thesis thus introduces
a methodology for a form of technology-downstreaming and highlights the potential of
probabilistic architecture for computation with future nanoscale MOSFETs