RF circulator structures via offset lithography

Further developments are reported of the conductive lithographic film (CLF) process in which components of radio-frequency circulators are fabricated economically via offset lithography. The performance of centre conductor elements printed from silver-loaded inks on polymer substrates is compared with that of conventional solid copper structures

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Modeling of reverse current effects in trench-based smart power technologies

The increase in complexity in todays automotive products is driven by the trend to implement new features in the area of safety, comfort and entertainment. This significantly raises the safety requirements of new ICs and the identification of possible sources of failures gains in priority. One of these failure sources is the injection of parasitic currents into the common substrate of a chip. This does not only occur during exceptions in the operation of the IC but also affects applications which require switching of inductive loads. The difficulty to handle substrate current injection originates from its nonlocality as it potentially influences the entire IC. In this thesis a point-to-point modeling scheme for Spice-based circuit simulation is proposed. It addresses parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. These models represent the three main components in the coupling path which are the forward biased diode at the perturbing device, the reverse biased diode at the susceptible node, and the intermediary common substrate of the chip. An automated layout extraction framework identifies the injectors of the minority carriers and the sensitive devices. Additionally, it determines the relevant parameters for the models. The curve fitting functions of the models are derived from calibrated TCAD simulations which are based on the measurement results of two dedicated test chips. The test chips were specifically designed to provide detailed analysis capabilities of this parasitic coupling effect. This led to a design which contains several different injector nodes and a large number of susceptible nodes spread over the entire area of the chip. Additionally, the chip incorporates the most commonly used layout-based guard structures to obtain an in-depth insight on their efficiency in recent BCD technologies. Based on the results obtained by measurements of the test chips the underlying physics of the coupling effect are discussed in detail. Minority carrier injection in the substrate is not much different to the operating principle of a bipolar transistor and the differences and similarities between them are presented. This forms the basis of the model development and explains how the equations of the Verilog-AMS models were derived. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Overview of CMOS process and design options for image sensor dedicated to space applications

With the growth of huge volume markets (mobile phones, digital cameras…) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35µm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques

Soft Gamma-ray Detector for the ASTRO-H Mission

ASTRO-H is the next generation JAXA X-ray satellite, intended to carry instruments with broad energy coverage and exquisite energy resolution. The Soft Gamma-ray Detector (SGD) is one of ASTRO-H instruments and will feature wide energy band (40-600 keV) at a background level 10 times better than the current instruments on orbit. SGD is complimentary to ASTRO-H's Hard X-ray Imager covering the energy range of 5-80 keV. The SGD achieves low background by combining a Compton camera scheme with a narrow field-of-view active shield where Compton kinematics is utilized to reject backgrounds. The Compton camera in the SGD is realized as a hybrid semiconductor detector system which consists of silicon and CdTe (cadmium telluride) sensors. Good energy resolution is afforded by semiconductor sensors, and it results in good background rejection capability due to better constraints on Compton kinematics. Utilization of Compton kinematics also makes the SGD sensitive to the gamma-ray polarization, opening up a new window to study properties of gamma-ray emission processes. The ASTRO-H mission is approved by ISAS/JAXA to proceed to a detailed design phase with an expected launch in 2014. In this paper, we present science drivers and concept of the SGD instrument followed by detailed description of the instrument and expected performance.Comment: 17 pages, 15 figures, Proceedings of the SPIE Astronomical Instrumentation "Space Telescopes and Instrumentation 2010: Ultraviolet to Gamma Ray

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements