Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

VCSEL Equivalent Circuits and Silicon Photonics Integration

The vertical-cavity surface-emitting laser (VCSEL) is a light source of great importance for numerous industrial and consumer products. The main application areas are datacom and sensing. The datacom industry uses GaAs-based VCSELs for optical interconnects, the short-reach fiber optical communication links used to transfer large amounts of data at high rates between units within data centers and supercomputers. In the area of sensing, VCSELs are largely used in consumer products such as smart phones (e.g. face ID and camera auto focus), computer mice, and automobiles (e.g. gesture recognition and LIDAR for autonomous driving).In this work, an advanced physics-based equivalent circuit model for datacom VCSELs has been developed. The model lends itself to co-design and co-optimization with driver and receiver ICs, thereby enabling higher data rate transceivers with bandwidth limited VCSELs and photodiodes. The model also facilitates an understanding of how each physical process within the VCSEL affects the VCSEL static and dynamic performance. It has been applied to study the impact of carrier transport and capture on VCSEL dynamics.The work also includes micro-transfer-printing of GaAs-based single-mode VCSELs on silicon nitride photonic integrated circuits (PICs). Such PICs are increasingly used for e.g. compact and highly functional bio-photonic sensors. Transfer printing of VCSELs enables the much-needed on-PIC integration of power efficient light sources. The bottom-emitting VCSELs are printed above grating couplers on the PIC and optical feedback is used to control the polarization for efficient coupling to the silicon nitride waveguide. Wavelength tuning, as required by the bio-sensing application, is achieved by direct current modulation

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Cryogenic Neuromorphic Hardware

The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, Neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insights to circumvent these challenges for the future progression of research

Microwave techniques and applications for semiconductor quantum dot mode-locked lasers

Semiconductor mode-locked lasers (MLLs) are important as compact and cost-effective sources of picosecond or sub-picosecond optical pulses with moderate peak powers. They have potential use in various fields including optical interconnects for clock distribution at an inter-chip/intra-chip level as well as high bit-rate optical time division multiplexing (OTDM), diverse waveform generation, and microwave signal generation. However, there are still several challenges to conquer for engineering applications. Semiconductor MLLs sources have generally not been able to match the noise performance and pulse quality of the best solid-state mode-locked lasers. For improving the characteristics of semiconductor mode-locked lasers, research on both the material/device design and stabilization mechanism is necessary. In this dissertation, by extending the net-gain modulation phasor approach based on a microwave photonics perspective, a convenient, yet powerful analytical model is derived and experimentally verified for the cavity design of semiconductor two-section passive MLLs. This model will also be useful in designing the next generation quantum dot (QD) MLL capable of stable operation from 20°C to 100°C for optical interconnects applications. The compact optical generation of microwave signals using a monolithic passive QD MLL is investigated. Relevant equations for the efficient conversion of electrical to optical to electrical (EOE) energy are derived and the device principles are described. In order to verify the function of a QD MLL as an RF signal generator, the integration with a rectangular patch antenna system is also studied. Furthermore, combined with the reconfigurable function, the multi-section QD MLL will be a promising candidate of the compact, efficient RF signal source in wireless, beam steering, and satellite communication applications. The noise performance is a key element for semiconductor MLLs in OTDM communications. The external stabilization methods to improve the timing stability in passive MLLs have been studied and an all-microwave measurement technique has also been developed to determine the pulse-to-pulse rms timing jitter. Compared to the conventional optical cross-correlation technique, the new method provides an alternative and simple approach to characterize the timing jitter in a passive MLL. The average pulse-to-pulse rms timing jitter is reduced to 32 fs/cycle under external optical feedback stabilization

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Bidirectional multi-photon communication between remote superconducting nodes

Quantum communication testbeds provide a useful resource for experimentally investigating a variety of communication protocols. Here we demonstrate a superconducting circuit testbed with bidirectional multi-photon state transfer capability using time-domain shaped wavepackets. The system we use to achieve this comprises two remote nodes, each including a tunable superconducting transmon qubit and a tunable microwave-frequency resonator, linked by a 2 m-long superconducting coplanar waveguide, which serves as a transmission line. We transfer both individual and superposition Fock states between the two remote nodes, and additionally show that this bidirectional state transfer can be done simultaneously, as well as used to entangle elements in the two nodes.Comment: Main Paper has 6 pages, 4 figures. Supplementary has 14 pages, 16 figures, 2 table

Superconducting Logic Circuits Operating With Reciprocal Magnetic Flux Quanta

Complimentary Medal-Oxide Semiconductor (CMOS) technology is expected to soon reach its fundamental limits of operation. The fundamental speed limit of about 4 GHz has already effectively been sidestepped by parallelization. This increases raw processing power but does nothing to improve power dissipation or latency. One approach for increasing computing performance involves using superconducting digital logic circuits. In this thesis I describe a new kind of superconducting logic, invented by Quentin Herr at Northrop Grumman, which uses reciprocal pairs of quantized single magnetic flux pulses to encode classical bits. In Reciprocal Quantum Logic (RQL) the data is encoded in integer units of the magnetic flux quantum. RQL gates operate without the bias resistors of previous superconducting logic families and dissipate several orders of magnitude less power. I demonstrate the basic operation of key RQL gates (AndOr, AnotB, Set/Reset) and show their self-resetting properties. Together, these gates form a universal logic set and provide memory capabilities. Experiments measuring the bit error rate of the AndOr gate extrapolated a minimum BER of 10-480 and a BER of 10-44 with 30% margins on flux biasing. I describe an analytic timing model for RQL gates which demonstrates the self-correcting timing features. From this model I derive equations for the timing behavior and operating limits. Using this timing model I ran simulations to determine correction factions for more accurate predictions at higher frequencies. Using these results, I also develop Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) models to describe the combinational logic of RQL gates. To test the timing predictions of the timing model, I performed three experiments on Nb/AlOx/Nb circuits at 4.2 K. The first measured the time of output. The second measured the operating margins of the circuit. The third measured the maximum frequency of operation for RQL circuits. Together, these three experiments showed quantitative agreement with the model for the timing output, qualitative agreement with the limits of operation, and a projected speed limit of 50 GHz for the Hypres 4.5 kA/cm2 process. To power RQL circuits I describe a new design for power splitters and combiners which minimize standing waves. I describe a new kind of Wilkinson power splitter which required numerical optimization but proved to be adequate. I experimentally tested two new designs of the power splitter. Both showed less than 10% variation in standing waves between power splitter and combiner, making it adequate for RQL circuits. I also compared these results with the S-parameters of the power network, which also indicated that the design was adequate for RQL circuits. Finally, I tested an 8-bit Kogge-Stone architecture carry-look ahead adder designed using VHDL models. The adder contained 815 Josephson junctions and was fully functional at 6.21 GHz with a latency of 1.25 clock cycles. The adder produced the correct logical output, had a measured optimal operating point within 8% of the optimal simulated operating point, and measured power margins of 1 dB. It operated best at the designed clock amplitude of 0.88Ic and dissipated 0.570 mW of power