Accurate spectral testing without accurate instrumentation

Analog-to-digital converters (ADCs) are becoming increasingly common in many systems in integrated circuits. Spectral testing is widely used to test the dynamic linearity performance of ADCs and waveform generators. With improvements in the performance of ADCs, it is becoming an expensive and challenging task to perform spectral testing using standard methods because of the requirement that the test instrumentation environment must satisfy several stringent conditions. In order to address these challenges and to decrease the test cost, in this dissertation, four new algorithms are proposed to perform accurate spectral testing of ADCs by relaxing three conditions required for standard spectral testing methods. The first method developed is relaxing the requirements on precise control of coherent sampling and input signal amplitude. The efficiency and accuracy of this method is similar to the straightforward FFT, but it can simultaneously handle amplitude clipping and noncoherent sampling. By replacing a noncoherent and clipped fundamental with a coherent and unclipped one, correct spectral specifications can be obtained. Both simulation and measurement results validated the proposed method. The second algorithm can simultaneously perform the linearity test and the spectral test with only one-time data acquisition. Targeted for realizing the cotest of linearity and spectral performance under noncoherent sampling and amplitude clipping, a new accurate method for identifying the noncoherent and clipped fundamental is introduced. The residue after removing the identified fundamental from raw data is used to obtain the linearity and spectral characterizations. Simulation and measurement results against the standard test methods collaborate to validate the accuracy and robustness of the new solution. The third method proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying a simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics need not be known before the processing. The algorithm is robust enough that nonharmonic spurs do not affect the estimation result. Using the proposed algorithm, specifications of the ADC under test can be obtained without the jitter effect. Simulation results of ADCs with different resolutions show the functionality and accuracy of the method. The last method is developed to accurately estimate the SNR with sampling clock jitter. This method does not require a precise sampling clock and thus reduces the test cost. The ADC output sequence is separated into two segments. By analyzing the difference of the two segments, the RMS of jitter and the noise power are estimated, and then the SNR is obtained. Simulation and measurement results against the standard test methods collaborate to validate the accuracy and robustness of the new solution

Accurate Jitter Decomposition in High-Speed Links

In a high-speed digital communication system, jitter performance plays a crucial role in Bit-Error Rate (BER). It is important to accurately derive each type of jitter as well as total jitter (TJ) and to identify the root causes of jitter by jitter decomposition. In this work, we propose new jitter decomposition techniques in high-speed links testing. The background of jitter decomposition is described in chapter 1. In chapter 2, duty cycle distortion jitter amplification is introduced. As channel loss results in both ISI and jitter amplification, DCD amplification is a big concern in high-speed links. The derivation of a formula of DCD amplification for data channels is included and the calculation result matches the time-domain simulation in the system. Chapter 3 provides an accurate jitter decomposition algorithm using Least Squares (LS) which simultaneously separates ISI, RJ, and PJ. A new time domain ISI model is proposed, which is faster and more accurate than the conventional ISI model. This algorithm obtains the estimated individual jitter component value with fine accuracy by using less samples of total jitter data compared with conventional methods. The simulation and measurement show the accuracy and efficiency of this algorithm with less data samples. In chapter 4, a low-cost comparator-based jitter decomposition algorithm is proposed. Instead of using TIE jitter sequence to decompose, it uses a low cost and simple comparator network to identify the deviation of current sampling positions from the ideal sampling positions to represent the TIE. It simultaneously separates ISI, DCD, and PJ and can achieve similar accuracy compared to the instrument test. Both the simulation and measurement show the decomposition algorithm with great accuracy and efficiency. In chapter 5, a low cost and simple dithering method to improve the test of linearity of analog-to-digital converter (ADC) is proposed. This method exhibits an improvement and enhancement for the ultra-fast segmented model identification of linearity error (uSMILE) algorithm which reduces 99% of the test time compared to the conventional method. In this study, we proposed three types of distribution dithering methods adding to the ramp input signal to reduce the estimation error when uSMILE was applied in low resolution ADCs. The fix pattern distribution was proved as the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fix-pattern distributions. Both the simulation results and hardware measurement indicate that the estimation error can be significantly reduced in 12-bit SAR ADC with effective dithering

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

Optical sampling and metrology using a soliton-effect compression pulse source

A low jitter optical pulse source for applications including optical sampling and optical metrology was modelled and then experimentally implemented using photonic components. Dispersion and non-linear fibre effects were utilised to compress a periodic optical waveform to generate pulses of the order of 10 picoseconds duration, via soliton-effect compression. Attractive features of this pulse source include electronically tuneable repetition rates greater than 1.5 GHz, ultra-short pulse duration (10-15 ps), and low timing jitter as measured by both harmonic analysis and single-sideband (SSB) phase noise measurements. The experimental implementation of the modelled compression scheme is discussed, including the successful removal of stimulated Brillouin scattering (SBS) through linewidth broadening by injection dithering or phase modulation. Timing jitter analysis identifies many unwanted artefacts generated by the SBS suppression methods, hence an experimental arrangement is devised (and was subsequently patented) which ensures that there are no phase modulation spikes present on the SSB phase noise spectrum over the offset range of interest for optical sampling applications, 10Hz-Nyquist. It is believed that this is the first detailed timing jitter study of a soliton-effect compression scheme. The soliton-effect compression pulses are then used to perform what is believed to be the first demonstration of optical sampling using this type of pulse source. The pulse source was also optimised for use in a novel optical metrology (range finding) system, which is being developed and patented under European Space Agency funding as an enabling technology for formation flying satellite missions. This new approach to optical metrology, known as Scanning Interferometric Pulse Overlap Detection (SIPOD), is based on scanning the optical pulse repetition rate to find the specific frequencies which allow the return pulses from the outlying satellite, i.e. the measurement arm, to overlap exactly with a reference pulse set on the hub satellite. By superimposing a low frequency phase modulation onto the optical pulse train, it is possible to detect the pulse overlap condition using conventional heterodyne detection. By rapidly scanning the pulse repetition rate to find two frequencies which provide the overlapping pulse condition, high precision optical pulses can be used to provide high resolution unambiguous range information, using only relatively simple electronic detection circuitry. SIPOD’s maximum longitudinal range measurement is limited only by the coherence length of the laser, which can be many tens of kilometres. Range measurements have been made to better than 10 microns resolution over extended duration trial periods, at measurement update rates of up to 470 Hz. This system is currently scheduled to fly on ESA’s PROBA-3 mission in 2012 to measure the intersatellite spacing for a two satellite coronagraph instrument. In summary, this thesis is believed to present three novel areas of research: the first detailed jitter characterisation of a soliton-effect compression source, the first optical sampling using such a compression source, and a novel optical metrology range finding system, known as SIPOD, which utilises the tuneable repetition rate and highly stable nature of the compression source pulses

Temporal-Coded Deep Spiking Neural Network with Easy Training and Robust Performance

Spiking neural network (SNN) is interesting both theoretically and practically because of its strong bio-inspiration nature and potentially outstanding energy efficiency. Unfortunately, its development has fallen far behind the conventional deep neural network (DNN), mainly because of difficult training and lack of widely accepted hardware experiment platforms. In this paper, we show that a deep temporal-coded SNN can be trained easily and directly over the benchmark datasets CIFAR10 and ImageNet, with testing accuracy within 1% of the DNN of equivalent size and architecture. Training becomes similar to DNN thanks to the closed-form solution to the spiking waveform dynamics. Considering that SNNs should be implemented in practical neuromorphic hardwares, we train the deep SNN with weights quantized to 8, 4, 2 bits and with weights perturbed by random noise to demonstrate its robustness in practical applications. In addition, we develop a phase-domain signal processing circuit schematic to implement our spiking neuron with 90% gain of energy efficiency over existing work. This paper demonstrates that the temporal-coded deep SNN is feasible for applications with high performance and high energy efficient

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling- and interleaving-based systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process

Low Noise And Low Repetition Rate Semiconductor-based Mode-locked Lasers

The topic of this dissertation is the development of low repetition rate and low noise semiconductor-based laser sources with a focus on linearly chirped pulse laser sources. In the past decade chirped optical pulses have found a plethora of applications such as photonic analogto-digital conversion, optical coherence tomography, laser ranging, etc. This dissertation analyzes the aforementioned applications of linearly chirped pulses and their technical requirements, as well as the performance of previously demonstrated chirped pulse laser sources. Moreover, the focus is shifted to a specific application of the linearly chirped pulses, timestretched photonic analog-to-digital conversion (TS ADC). The challenges of surpassing the speeds of current electronic converters are discussed, while the need for low noise linearly chirped pulse lasers becomes apparent for the realization of TS ADC. The experimental research addresses the topic of low noise chirped pulse generation in three distinct ways. First, a chirped pulse (Theta) laser with an intra-cavity Fabry-Pérot etalon and a long-term referencing mechanism is developed that results in the reduction of the pulse-topulse energy noise. Noise suppression of \u3e 15 times is demonstrated. Moreover, an optical frequency comb with spacing equal to the repetition rate (≈100 MHz) is generated using the etalon, resulting in the first reported demonstration of a system operating in the sub-GHz regime based on semiconductor gain. The path for the development of the Theta laser was laid by the precise characterization of the etalon used in this laser cavity design. A narrow linewidth laser is used in conjunction with an acousto-optic modulator externally swept for measuring the etalon\u27s iv free spectral range with a sub-Hz precision, or 10 parts per billion. Furthermore, the measurement of the etalon long-term drift and birefringence lead to the development of a modified intra-cavity Hänsch-Couillaud locking mechanism for the Theta laser. Moreover, an external feed-forward system was demonstrated that aimed at increasing the temporal/spectral uniformity of the optical pulses. A complete characterization of the system is demonstrated. On a different series of experiments, the pulses emitted by an ultra-low noise but high repetition rate mode-locked laser were demultiplexed resulting in a low repetition rate pulse train. Experimental investigation of the noise properties of the laser proved that they are preserved during the demultiplexing process. The noise of the electrical gate used in this experiment is also investigated which led into the development of a more profound understanding of the electrical noise of periodical pulses and a mechanism of measuring their noise. The appendices in this dissertation provide additional material used for the realization of the main research focus of the dissertation. Measurements of the group delay of the etalon used in the Theta laser are presented in order to demonstrate the limiting factors for the development of this cavity design. The description of a balancing routine is presented, that was used for expanding the dynamic range of intra-cavity active variable delay. At last, the appendix presents the calculations regarding the contribution of various parameters in the limitations of analog-todigital conversion