Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAALO03-86-K-0002)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI SemiconductorU.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryDARPA/U.S. Navy - Office of Naval Research (Contract N00014-80-C-0622)DARPA/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)National Science Foundation (Grant ECS-83-10941)AT&T Bell Laboratorie

Theoretical and practical aspects of parallel numerical algorithms for initial value problems, with applications

Includes bibliographical references (p. 80-82).Supported by IBM Corp., and by a AEA/Dynatech faculty development fellowship. Supported by the Defense Advanced Research Projects Agency, under the Office of Naval Research. N00014-91-J-1698 Supported by a National Science Foundation. MIP-88-14612Andrew Lumsdaine

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

Modeling and Simulation of Nonlinearly Loaded Electromagnetic Systems via Reduced Order Models - A Case Study: Energy Selective Surfaces

L'abstract è presente nell'allegato / the abstract is in the attachmen

The Use of Parallel Processing in VLSI Computer-Aided Design Application

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / 87-DP-10

Longitudinal Partitioning Waveform Relaxation Methods For The Analysis of Transmission Line Circuits

Three research projects are presented in this manuscript. Projects one and two describe two waveform relaxation algorithms (WR) with longitudinal partitioning for the time-domain analysis of transmission line circuits. Project three presents theoretical results about the convergence of WR for chains of general circuits. The first WR algorithm uses a assignment-partition procedure that relies on inserting external series combinations of positive and negative resistances into the circuit to control the speed of convergence of the algorithm. The convergence of the subsequent WR method is examined, and fast convergence is cast as a generic optimization problem in the frequency-domain. An automatic suboptimal numerical solution of the min-max problem is presented and a procedure to construct its objective function is suggested. Numerical examples illustrate the parallelizability and good scaling of the WR algorithm and point out to the limitation of resistive coupling. In the second WR algorithm, resistances from the previous insertion are replaced with dissipative impedances to address the slow convergence of standard resistive coupling of the first algorithm for low-loss highly reactive circuits. The pertinence and feasibility of impedance coupling are demonstrated and the properties of the subsequent WR method are studied. A new coupling strategy proposes judicious approximations of the optimal convergence conditions for faster speed of convergence. The proposed strategy avoids the difficult problem of optimisation and uses coarse macromodeling of the transmission line to construct approximations with delay under circuit form. Numerical examples confirm a superior speed of convergence which leads to further runtime saving. Finally, new results concerning the nilpotent WR algorithm are presented for chains of circuits when dissipative coupling is used. It is shown that optimal local convergence is necessary to achieve the optimal WR algorithm. However, the converse is not correct: the WR algorithm with optimal local convergences factors can be nilpotent yet not optimal or even be non-nilpotent at all. The second analysis concerns resistive coupling. It is demonstrated that WR always converges for chains circuits. More precisely, it is shown that WR will converge independently of the length of the chain when this late is made of identical symmetric circuits

Hybrid Analog-Digital Co-Processing for Scientific Computation

In the past 10 years computer architecture research has moved to more heterogeneity and less adherence to conventional abstractions. Scientists and engineers hold an unshakable belief that computing holds keys to unlocking humanity's Grand Challenges. Acting on that belief they have looked deeper into computer architecture to find specialized support for their applications. Likewise, computer architects have looked deeper into circuits and devices in search of untapped performance and efficiency. The lines between computer architecture layers---applications, algorithms, architectures, microarchitectures, circuits and devices---have blurred. Against this backdrop, a menagerie of computer architectures are on the horizon, ones that forgo basic assumptions about computer hardware, and require new thinking of how such hardware supports problems and algorithms. This thesis is about revisiting hybrid analog-digital computing in support of diverse modern workloads. Hybrid computing had extensive applications in early computing history, and has been revisited for small-scale applications in embedded systems. But architectural support for using hybrid computing in modern workloads, at scale and with high accuracy solutions, has been lacking. I demonstrate solving a variety of scientific computing problems, including stochastic ODEs, partial differential equations, linear algebra, and nonlinear systems of equations, as case studies in hybrid computing. I solve these problems on a system of multiple prototype analog accelerator chips built by a team at Columbia University. On that team I made contributions toward programming the chips, building the digital interface, and validating the chips' functionality. The analog accelerator chip is intended for use in conjunction with a conventional digital host computer. The appeal and motivation for using an analog accelerator is efficiency and performance, but it comes with limitations in accuracy and problem sizes that we have to work around. The first problem is how to do problems in this unconventional computation model. Scientific computing phrases problems as differential equations and algebraic equations. Differential equations are a continuous view of the world, while algebraic equations are a discrete one. Prior work in analog computing mostly focused on differential equations; algebraic equations played a minor role in prior work in analog computing. The secret to using the analog accelerator to support modern workloads on conventional computers is that these two viewpoints are interchangeable. The algebraic equations that underlie most workloads can be solved as differential equations, and differential equations are naturally solvable in the analog accelerator chip. A hybrid analog-digital computer architecture can focus on solving linear and nonlinear algebra problems to support many workloads. The second problem is how to get accurate solutions using hybrid analog-digital computing. The reason that the analog computation model gives less accurate solutions is it gives up representing numbers as digital binary numbers, and instead uses the full range of analog voltage and current to represent real numbers. Prior work has established that encoding data in analog signals gives an energy efficiency advantage as long as the analog data precision is limited. While the analog accelerator alone may be useful for energy-constrained applications where inputs and outputs are imprecise, we are more interested in using analog in conjunction with digital for precise solutions. This thesis gives novel insight that the trick to do so is to solve nonlinear problems where low-precision guesses are useful for conventional digital algorithms. The third problem is how to solve large problems using hybrid analog-digital computing. The reason the analog computation model can't handle large problems is it gives up step-by-step discrete-time operation, instead allowing variables to evolve smoothly in continuous time. To make that happen the analog accelerator works by chaining hardware for mathematical operations end-to-end. During computation analog data flows through the hardware with no overheads in control logic and memory accesses. The downside is then the needed hardware size grows alongside problem sizes. While scientific computing researchers have for a long time split large problems into smaller subproblems to fit in digital computer constraints, this thesis is a first attempt to consider these divide-and-conquer algorithms as an essential tool in using the analog model of computation. As we enter the post-Moore’s law era of computing, unconventional architectures will offer specialized models of computation that uniquely support specific problem types. Two prominent examples are deep neural networks and quantum computers. Recent trends in computer science research show these unconventional architectures will soon have broad adoption. In this thesis I show another specialized, unconventional architecture is to use analog accelerators to solve problems in scientific computing. Computer architecture researchers will discover other important models of computation in the future. This thesis is an example of the discovery process, implementation, and evaluation of how an unconventional architecture supports specialized workloads

Simulated Annealing with min-cut and greedy perturbations

Custom integrated circuit design requires an ever increasing number of elements to be placed on a physical die. The process of searching for an optimal solution is NP-hard so heuristics are required to achieve satisfactory results under time constraints. Simulated Annealing is an algorithm which uses randomly generated perturbations to adjust a single solution. The effect of a generated perturbation is examined by a cost function which evaluates the solution. If the perturbation decreases the cost, it is accepted. If it increases the cost, it is accepted probabilistically. Such an approach allows the algorithm to avoid local minima and find satisfactory solutions. One problem faced by Simulated Annealing is that it can take a very large number of iterations to reach a desired result. Greedy perturbations use knowledge of the system to generate solutions which may be satisfactory after fewer iterations than non-greedy, however previous work has indicated that the exclusive use of greedy perturbations seems to result in a solution constrained to local minima. Min-cut is a procedure in which a graph is split into two pieces with the least interconnection possible between them. Using this with a placement problem helps to recognize components which belong to the same functional unit and thus enhance results of Simulated Annealing. The feasibility of this approach has been assessed. Hardware, through parallelization, can be used to increase the performance of algorithms by decreasing runtime. The possibility of increased performance motivated the exploration of the ability to model greedy perturbations in hardware. The use of greedy perturbations while avoiding local minima was also explored

The Sixth Copper Mountain Conference on Multigrid Methods, part 2

The Sixth Copper Mountain Conference on Multigrid Methods was held on April 4-9, 1993, at Copper Mountain, Colorado. This book is a collection of many of the papers presented at the conference and so represents the conference proceedings. NASA Langley graciously provided printing of this document so that all of the papers could be presented in a single forum. Each paper was reviewed by a member of the conference organizing committee under the coordination of the editors. The multigrid discipline continues to expand and mature, as is evident from these proceedings. The vibrancy in this field is amply expressed in these important papers, and the collection clearly shows its rapid trend to further diversity and depth