Thread-Modular Static Analysis for Relaxed Memory Models

We propose a memory-model-aware static program analysis method for accurately analyzing the behavior of concurrent software running on processors with weak consistency models such as x86-TSO, SPARC-PSO, and SPARC-RMO. At the center of our method is a unified framework for deciding the feasibility of inter-thread interferences to avoid propagating spurious data flows during static analysis and thus boost the performance of the static analyzer. We formulate the checking of interference feasibility as a set of Datalog rules which are both efficiently solvable and general enough to capture a range of hardware-level memory models. Compared to existing techniques, our method can significantly reduce the number of bogus alarms as well as unsound proofs. We implemented the method and evaluated it on a large set of multithreaded C programs. Our experiments showthe method significantly outperforms state-of-the-art techniques in terms of accuracy with only moderate run-time overhead.Comment: revised version of the ESEC/FSE 2017 pape

Abstracting Call-Stacks for Interprocedural Verification of Imperative Programs

We address in this paper the verification of imperative programs with recursion. Our approach consists in using abstract interpretation to relate the standard semantics of imperative programs to an abstract semantics, by the mean of a Galois connection, and then to resort to intraprocedural techniques, which can be applied on the abstract semantics. This approach allows the reuse of classical intraprocedural techniques with few modifications, generalises existing approaches to interprocedural analysis and offers additional flexibility, as it keeps substantial information on the call-stack of the analysed program