Security and reliability analysis of a two-way half-duplex wireless relaying network using partial relay selection and hybrid TPSR energy harvesting at relay nodes

In recent years, physical layer security has been considered as an effective method to enhance the information security beside the cryptographic techniques that are used in upper layers. In this paper, we provide the security analysis for a two-way relay network, where the two sources can only communicate through the intermediate relay nodes. In particular, we consider the scenario that there is an eavesdropper in the vicinity of one source node. Both reliability and security aspects are taken into consideration in our work. To enhance the reliability of communication, the intermediate relays are supplied with the energy harvested from the sources radio frequency (RF) signals using hybrid time-switching and power splitting (TPSR) protocol. Also, we apply the relay selection technique to select the best relay for the information exchange between two sources. Regarding security, the secrecy of information is improved with the help of friendly jammers nearby the eavesdropper. We provide the in-dept reliability and security analysis in terms of the closed-form expressions of the outage probability (OP) at the source nodes, the intercept probability (IP) at the eavesdropper, the secrecy outage probability (SOP), and the average secrecy capacity (ASC) of the system. Finally, the Monte Carlo simulations are also conducted to verify the correctness of our analysis and the effectiveness of the proposed scheme. Numerical results confirms that with the appropriate and feasible choices of involved parameters, both outage OP and IP can be kept at small values to guarantee the reliable and secure communication of the system.Web of Science818718118716

Energy Efficient VLSI Circuits for MIMO-WLAN

Mobile communication - anytime, anywhere access to data and communication services - has been continuously increasing since the operation of the first wireless communication link by Guglielmo Marconi. The demand for higher data rates, despite the limited bandwidth, led to the development of multiple-input multiple-output (MIMO) communication which is often combined with orthogonal frequency division multiplexing (OFDM). Together, these two techniques achieve a high bandwidth efficiency. Unfortunately, techniques such as MIMO-OFDM significantly increase the signal processing complexity of transceivers. While fast improvements in the integrated circuit (IC) technology enabled to implement more signal processing complexity per chip, large efforts had and have to be done for novel algorithms as well as for efficient very large scaled integration (VLSI) architectures in order to meet today's and tomorrow's requirements for mobile wireless communication systems. In this thesis, we will present architectures and VLSI implementations of complete physical (PHY) layer application specific integrated circuits (ASICs) under the constraints imposed by an industrial wireless communication standard. Contrary to many other publications, we do not elaborate individual components of a MIMO-OFDM communication system stand-alone, but in the context of the complete PHY layer ASIC. We will investigate the performance of several MIMO detectors and the corresponding preprocessing circuits, being integrated into the entire PHY layer ASIC, in terms of achievable error-rate, power consumption, and area requirement. Finally, we will assemble the results from the proposed PHY layer implementations in order to enhance the energy efficiency of a transceiver. To this end, we propose a cross-layer optimization of PHY layer and medium access control (MAC) layer

ASIP design for multiuser MIMO broadcast precoding

Abstract This paper presents an application-specific instruction-set processor (ASIP) for multiuser multiple-input multiple-output (MU-MIMO) broadcast precoding. The ASIP is designed for a base station (BS) with four antennas to perform user scheduling and precoding. Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP. Several special function units (SFU) are designed to accelerate norm-based greedy user scheduling and minimum-mean square error (MMSE) precoding. We also program zero forcing dirty paper coding (ZF-DPC) to demonstrate the reusability of the ASIP. A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology