AER tools for Communications and Debugging

Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of instruments that would allow to: generate AER streams, monitor the output produced by neural chips and modify the spike stream produced by an emitting chip to adapt it to the requirements of the receiving elements. In this paper we present a set of tools that implement these functions developed in the CAVIAR EU projectUnión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C03-0

Spikes Monitors for FPGAs, an Experimental Comparative Study

In this paper we present and analyze two VHDL components for monitoring internal activity of spikes fired by silicon neurons inside FPGAs. These spikes monitors encode each spike according to the Address-Event Representation, sending them through a time multiplexed digital bus as discrete events, using different strategies. In order to study and analyze their behavior we have designed an experimental scenario, where diverse AER systems have been used to stimulate the spikes monitors and collect the output AER events, for later analysis. We have applied a battery of tests on both monitors in order to measure diverse features such as maximum spike load and AER event loss due to collisions.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Economía y Competitividad TEC2012-37868-C04-0

A USB3.0 FPGA Event-based Filtering and Tracking Framework for Dynamic Vision Sensors

Dynamic vision sensors (DVS) are frame-free sensors with an asynchronous variable-rate output that is ideal for hard real-time dynamic vision applications under power and latency constraints. Post-processing of the digital sensor output can reduce sensor noise, extract low level features, and track objects using simple algorithms that have previously been implemented in software. In this paper we present an FPGA-based framework for event-based processing that allows uncorrelated-event noise removal and real-time tracking of multiple objects, with dynamic capabilities to adapt itself to fast or slow and large or small objects. This framework uses a new hardware platform based on a Lattice FPGA which filters the sensor output and which then transmits the results through a super-speed Cypress FX3 USB microcontroller interface to a host computer. The packets of events and timestamps are transmitted to the host computer at rates of 10 Mega events per second. Experimental results are presented that demonstrate a low latency of 10us for tracking and computing the center of mass of a detected object.Ministerio de Economía y Competitividad TEC2012-37868-C04-0

From Vision Sensor to Actuators, Spike Based Robot Control through Address-Event-Representation

One field of the neuroscience is the neuroinformatic whose aim is to develop auto-reconfigurable systems that mimic the human body and brain. In this paper we present a neuro-inspired spike based mobile robot. From commercial cheap vision sensors converted into spike information, through spike filtering for object recognition, to spike based motor control models. A two wheel mobile robot powered by DC motors can be autonomously controlled to follow a line drown in the floor. This spike system has been developed around the well-known Address-Event-Representation mechanism to communicate the different neuro-inspired layers of the system. RTC lab has developed all the components presented in this work, from the vision sensor, to the robot platform and the FPGA based platforms for AER processing.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Junta de Andalucía P06-TIC-0141

Live Demonstration: real time objects tracking using a bio-inspired processing cascade architecture

This demonstration shows how a new bio-inspired processing cascade architecture is used for simultaneous objects tracking.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-02298Junta de Andalucía P06-TIC-0141

Visual Spike-based Convolution Processing with a Cellular Automata Architecture

this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution.Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141

Spike Processing on an Embedded Multi-task Computer: Image Reconstruction

There is an emerging philosophy, called Neuro-informatics, contained in the Artificial Intelligence field, that aims to emulate how living beings do tasks such as taking a decision based on the interpretation of an image by emulating spiking neurons into VLSI designs and, therefore, trying to re-create the human brain at its highest level. Address-Event-Representation (AER) is a communication protocol that has embedded part of the processing. It is intended to transfer spikes between bioinspired chips. An AER based system may consist of a hierarchical structure with several chips that transmit spikes among them in real-time, while performing some processing. There are several AER tools to help to develop and test AER based systems. These tools require the use of a computer to allow the higher level processing of the event information, reaching very high bandwidth at the AER communication level. We propose the use of an embedded platform based on a multi-task operating system to allow both, the AER communication and processing without the requirement of either a laptop or a computer. In this paper, we present and study the performance of a new philosophy of a frame-grabber AER tool based on a multi-task environment. This embedded platform is based on the Intel XScale processor which is governed by an embedded GNU/Linux system. We have connected and programmed it for processing Address-Event information from a spiking generator.Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Fully Digital AER Convolution Chip for Vision Processing

We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype.European Union IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-01Ministerio de Educación y Ciencia TEC2006-11730-C03-01Junta de Andalucía P06-TIC-0141

Real time multiple objects tracking based on a bioinspired processing cascade architecture

This paper presents a cascade architecture for bio-inspired information processing. We use AER (Address Event Representation) for transmitting and processing visual information provided by an asynchronous temporal contrast silicon retina. Using this architecture, we also present a multiple objects tracking algorithm; this algorithm is described in VHDL and implemented in a FPGA (Spartan II), which is part of the USB-AER platform developed by some of the authors.Junta de Andalucía P06-TIC-02298Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141

Red neuronal convolucional rápida sin fotogramas para reconocimientos de dígitos

Comunicación presentada al "XXVI Simposio de la URSI" celebrado en Leganés (España) del 7 al 9 de Septiembre del 2011.In this paper a bio-inspired six-layer convolutional network (ConvNet) non-frame based for digit recognition is shown. The system has been trained with the backpropagation algorithm using 32x32 images from the MNIST database. The system can be implemented with already physically available spike-based electronic devices. 10000 images have been coded into events separated 50ns to test the non-frame based ConvNet system. The simulation results have been obtained using actual performance figures for existing AER (Address Event Representation) hardware components. We provide simulation results of the system showing recognition delays of a few microseconds from stimulus onset with a recognition rate of 93%. The complete system consists of 30 convolution modules.Ministerio de Ciencia e Innovación (VULCANO) TEC2009-10639-C04-01Andalucía (Brain System) P06-TIC-0141