Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS

Fully integrated frequency-phase generators for a 6-18GHz wide-band phased-array receiver element are presented that generate 5-7GHz and 9-12GHz first LO signals with less than -95dBc/Hz phase noise at 100kHz offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3° resolution are generated and allow removal of systematic reference clock skew as well as accurate selection of the received signal phase. This frequency- and phase generation scheme was successfully demonstrated in a 6-18GHz receiver system configured as an electrical 4-element array

Oil cooling system for a gas turbine engine

A gas turbine engine fuel delivery and control system is provided with means to recirculate all fuel in excess fuel control requirements back to the aircraft fuel tank. This increases the fuel pump heat sink and decreases the pump temperature rise without the addition of valving other than normally employed. A fuel/oil heat exchanger and associated circuitry is provided to maintain the hot engine oil in heat exchange relationship with the cool engine fuel. Where anti-icing of the fuel filter is required, means are provided to maintain the fuel temperature entering the filter at or above a minimum level to prevent freezing thereof. In one embodiment, a divider valve is provided to take all excess fuel from either upstream or downstream of the fuel filter and route it back to the tanks, the ratio of upstream to downstream extraction being a function of fuel pump discharge pressure

A Programmable Frequency Divider Having a Wide Division Ratio Range, and Close-to-50% Output Duty-Cycle

In Radio Frequency (RF) integrated circuit design field, programmable dividers are getting more and more attentions in recent years. A programmable frequency divider can divide an input frequency by programmable ratios [1]. It is a key component of a frequency synthesizer. It also can be used to generate variable clock-signals for: switched-capacitor filters (SCFs), digital systems with different power-states, as well as multiple clock-signals on the same system-on-a-chip (SOC). These circuits need high performance programmable frequency dividers, operating at high frequencies and having wide division ratio ranges, with binary division ratio controls and 50% output duty-cycle. Different types of programmable frequency dividers are reviewed and compared. A programmable frequency divider with a wide division ratio range of (8 ~ 524287) has been reported [2]. Because the output duty-cycle of this reported divider is far from 50%, the circuit in [2] has very limited applications. The proposed design solves this problem, without compromising other advantages of the design in [2]. The proposed design is fabricated in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. The duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant, with different input frequencies from GHz down to kHz ranges, with different temperatures and power supply voltages. This thesis provides an explanation of the design details and test results. A Phase Locked-Loop (PLL) based frequency synthesizer can generate different output frequencies. A programmable frequency divider is an important component of this type of PLL. Since bandwidth is expensive, it is preferred to reduce the frequency channel distance of a frequency synthesizer. Using a fractional programmable divider, the frequency channel distance of a PLL can be reduced, without reducing the reference frequency or increasing the settling time of the PLL. A frequency synthesizer with a programmable fractional divider is designed and fabricated. A brief description of the PLL design and test results are presented in this dissertation

Amplifier for measuring low-level signals in the presence of high common mode voltage

A high common mode rejection differential amplifier wherein two serially arranged Darlington amplifier stages are employed and any common mode voltage is divided between them by a resistance network. The input to the first Darlington amplifier stage is coupled to a signal input resistor via an amplifier which isolates the input and presents a high impedance across this resistor. The output of the second Darlington stage is transposed in scale via an amplifier stage which has its input a biasing circuit which effects a finite biasing of the two Darlington amplifier stages

Phase control circuits using frequency multiplications for phased array antennas

A phase control coupling circuit for use with a phased array antenna is described. The coupling circuit includes a combining circuit which is coupled to a transmission line, a frequency multiplier circuit which is coupled to the combining circuit, and a recombining circuit which is coupled between the frequency multiplier circuit and phased array antenna elements. In a doubler embodiment, the frequency multiplier circuit comprises frequency doublers and the combining and recombining circuits comprise four-port hybrid power dividers. In a generalized embodiment, the multiplier circuit comprises frequency multiplier elements which multiply to the Nth power, the combining circuit comprises four-part hybrid power dividers, and the recombinding circuit comprises summing circuits

Design of a CO2 laser power control system for a Spacelab microgravity experiment

The surface tension driven convection experiment (STDCE) is a Space Transportation System flight experiment manifested to fly aboard the USML-1 Spacelab mission. A CO2 laser is used to heat a spot on the surface of silicone oil contained inside a test chamber. Several CO2 laser control systems were evaluated and the selected system will be interfaced with the balance of the experimental hardware to constitute a working engineering model. Descriptions and a discussion of these various design approaches are presented