SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression

[[abstract]]This paper presents a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one scan cell. Consequently, hardware overhead is much lower than cyclical scan chains (CSR). As the complexity of VLSI continues to grow, excessive power supply noise has become seriously. We propose a new compression scheme which smooth down the switching activity and reduce the test data volume simultaneously.[[conferencetype]]國際[[conferencelocation]]Taipei, Taiwa

B.O.G.G.L.E.S.: Boundary Optical GeoGraphic Lidar Environment System

The purpose of this paper is to describe a pseudo X-ray vision system that pairs a Lidar scanner with a visualization device. The system as a whole is referred to as B.O.G.G.L.E.S. There are several key factors that went into the development of this system and the background information and design approach are thoroughly described. B.O.G.G.L.E.S functionality is depicted through the use of design constraints and the analysis of test results. Additionally, many possible developments for B.O.G.G.L.E.S are proposed in the paper. This indicates that there are various avenues of improvement for this project that could be implemented in the future

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

GPU accelerated real-time multi-functional spectral-domain optical coherence tomography system at 1300 nm.

We present a GPU accelerated multi-functional spectral domain optical coherence tomography system at 1300 nm. The system is capable of real-time processing and display of every intensity image, comprised of 512 pixels by 2048 A-lines acquired at 20 frames per second. The update rate for all four images with size of 512 pixels by 2048 A-lines simultaneously (intensity, phase retardation, flow and en face view) is approximately 10 frames per second. Additionally, we report for the first time the characterization of phase retardation and diattenuation by a sample comprised of a stacked set of polarizing film and wave plate. The calculated optic axis orientation, phase retardation and diattenuation match well with expected values. The speed of each facet of the multi-functional OCT CPU-GPU hybrid acquisition system, intensity, phase retardation, and flow, were separately demonstrated by imaging a horseshoe crab lateral compound eye, a non-uniformly heated chicken muscle, and a microfluidic device. A mouse brain with thin skull preparation was imaged in vivo and demonstrated the capability of the system for live multi-functional OCT visualization