The Design and implementation of DCT/IDCT Chip with Novel Architecture

[[abstract]]In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz[[conferencetype]]國際[[booktype]]紙本[[conferencelocation]]Geneva, Switzerlan

Symmetric realization of DCT for multi-dimensional data compression

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High efficiency block coding techniques for image data.

by Lo Kwok-tung.Thesis (Ph.D.)--Chinese University of Hong Kong, 1992.Includes bibliographical references.ABSTRACT --- p.iACKNOWLEDGEMENTS --- p.iiiLIST OF PRINCIPLE SYMBOLS AND ABBREVIATIONS --- p.ivLIST OF FIGURES --- p.viiLIST OF TABLES --- p.ixTABLE OF CONTENTS --- p.xChapter CHAPTER 1 --- IntroductionChapter 1.1 --- Background - The Need for Image Compression --- p.1-1Chapter 1.2 --- Image Compression - An Overview --- p.1-2Chapter 1.2.1 --- Predictive Coding - DPCM --- p.1-3Chapter 1.2.2 --- Sub-band Coding --- p.1-5Chapter 1.2.3 --- Transform Coding --- p.1-6Chapter 1.2.4 --- Vector Quantization --- p.1-8Chapter 1.2.5 --- Block Truncation Coding --- p.1-10Chapter 1.3 --- Block Based Image Coding Techniques --- p.1-11Chapter 1.4 --- Goal of the Work --- p.1-13Chapter 1.5 --- Organization of the Thesis --- p.1-14Chapter CHAPTER 2 --- Block-Based Image Coding TechniquesChapter 2.1 --- Statistical Model of Image --- p.2-1Chapter 2.1.1 --- One-Dimensional Model --- p.2-1Chapter 2.1.2 --- Two-Dimensional Model --- p.2-2Chapter 2.2 --- Image Fidelity Criteria --- p.2-3Chapter 2.2.1 --- Objective Fidelity --- p.2-3Chapter 2.2.2 --- Subjective Fidelity --- p.2-5Chapter 2.3 --- Transform Coding Theroy --- p.2-6Chapter 2.3.1 --- Transformation --- p.2-6Chapter 2.3.2 --- Quantization --- p.2-10Chapter 2.3.3 --- Coding --- p.2-12Chapter 2.3.4 --- JPEG International Standard --- p.2-14Chapter 2.4 --- Vector Quantization Theory --- p.2-18Chapter 2.4.1 --- Codebook Design and the LBG Clustering Algorithm --- p.2-20Chapter 2.5 --- Block Truncation Coding Theory --- p.2-22Chapter 2.5.1 --- Optimal MSE Block Truncation Coding --- p.2-24Chapter CHAPTER 3 --- Development of New Orthogonal TransformsChapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Weighted Cosine Transform --- p.3-4Chapter 3.2.1 --- Development of the WCT --- p.3-6Chapter 3.2.2 --- Determination of a and β --- p.3-9Chapter 3.3 --- Simplified Cosine Transform --- p.3-10Chapter 3.3.1 --- Development of the SCT --- p.3-11Chapter 3.4 --- Fast Computational Algorithms --- p.3-14Chapter 3.4.1 --- Weighted Cosine Transform --- p.3-14Chapter 3.4.2 --- Simplified Cosine Transform --- p.3-18Chapter 3.4.3 --- Computational Requirement --- p.3-19Chapter 3.5 --- Performance Evaluation --- p.3-21Chapter 3.5.1 --- Evaluation using Statistical Model --- p.3-21Chapter 3.5.2 --- Evaluation using Real Images --- p.3-28Chapter 3.6 --- Concluding Remarks --- p.3-31Chapter 3.7 --- Note on Publications --- p.3-32Chapter CHAPTER 4 --- Pruning in Transform Coding of ImagesChapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- "Direct Fast Algorithms for DCT, WCT and SCT" --- p.4-3Chapter 4.2.1 --- Discrete Cosine Transform --- p.4-3Chapter 4.2.2 --- Weighted Cosine Transform --- p.4-7Chapter 4.2.3 --- Simplified Cosine Transform --- p.4-9Chapter 4.3 --- Pruning in Direct Fast Algorithms --- p.4-10Chapter 4.3.1 --- Discrete Cosine Transform --- p.4-10Chapter 4.3.2 --- Weighted Cosine Transform --- p.4-13Chapter 4.3.3 --- Simplified Cosine Transform --- p.4-15Chapter 4.4 --- Operations Saved by Using Pruning --- p.4-17Chapter 4.4.1 --- Discrete Cosine Transform --- p.4-17Chapter 4.4.2 --- Weighted Cosine Transform --- p.4-21Chapter 4.4.3 --- Simplified Cosine Transform --- p.4-23Chapter 4.4.4 --- Generalization Pruning Algorithm for DCT --- p.4-25Chapter 4.5 --- Concluding Remarks --- p.4-26Chapter 4.6 --- Note on Publications --- p.4-27Chapter CHAPTER 5 --- Efficient Encoding of DC Coefficient in Transform Coding SystemsChapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- Minimum Edge Difference (MED) Predictor --- p.5-3Chapter 5.3 --- Performance Evaluation --- p.5-6Chapter 5.4 --- Simulation Results --- p.5-9Chapter 5.5 --- Concluding Remarks --- p.5-14Chapter 5.6 --- Note on Publications --- p.5-14Chapter CHAPTER 6 --- Efficient Encoding Algorithms for Vector Quantization of ImagesChapter 6.1 --- Introduction --- p.6-1Chapter 6.2 --- Sub-Codebook Searching Algorithm (SCS) --- p.6-4Chapter 6.2.1 --- Formation of the Sub-codebook --- p.6-6Chapter 6.2.2 --- Premature Exit Conditions in the Searching Process --- p.6-8Chapter 6.2.3 --- Sub-Codebook Searching Algorithm --- p.6-11Chapter 6.3 --- Predictive Sub-Codebook Searching Algorithm (PSCS) --- p.6-13Chapter 6.4 --- Simulation Results --- p.6-17Chapter 6.5 --- Concluding Remarks --- p.5-20Chapter 6.6 --- Note on Publications --- p.6-21Chapter CHAPTER 7 --- Predictive Classified Address Vector Quantization of ImagesChapter 7.1 --- Introduction --- p.7-1Chapter 7.2 --- Optimal Three-Level Block Truncation Coding --- p.7-3Chapter 7.3 --- Predictive Classified Address Vector Quantization --- p.7-5Chapter 7.3.1 --- Classification of Images using Three-level BTC --- p.7-6Chapter 7.3.2 --- Predictive Mean Removal Technique --- p.7-8Chapter 7.3.3 --- Simplified Address VQ Technique --- p.7-9Chapter 7.3.4 --- Encoding Process of PCAVQ --- p.7-13Chapter 7.4 --- Simulation Results --- p.7-14Chapter 7.5 --- Concluding Remarks --- p.7-18Chapter 7.6 --- Note on Publications --- p.7-18Chapter CHAPTER 8 --- Recapitulation and Topics for Future InvestigationChapter 8.1 --- Recapitulation --- p.8-1Chapter 8.2 --- Topics for Future Investigation --- p.8-3REFERENCES --- p.R-1APPENDICESChapter A. --- Statistics of Monochrome Test Images --- p.A-lChapter B. --- Statistics of Color Test Images --- p.A-2Chapter C. --- Fortran Program Listing for the Pruned Fast DCT Algorithm --- p.A-3Chapter D. --- Training Set Images for Building the Codebook of Standard VQ Scheme --- p.A-5Chapter E. --- List of Publications --- p.A-

Distributed arithmetic architecture for the discrete cosine transform

The Discrete Cosine Transform is used in many image and video compression standards. Many methods have been developed for efficiently computing the Discrete Cosine Transform including flowgraph algorithms, distributed arithmetic and two-dimensional decompositions. A new architecture based on distributed arithmetic is presented for computing the Discrete Cosine Transform and it's inverse. The main objective of the design is to minimize the area of the VLSI implementation while maintaining the throughput necessary for video and image compression standards such as MPEG and JPEG. Several improvements have been made compared to previously published distributed arithmetic architectures. These include elimination of four lookup tables and implementation of the lookup tables using logic instead of ROM. A model of the proposed architecture was written in C. The model was used to verify the accuracy of the architecture and to do JPEG compression on a series of test images. Behavioral simulations were performed with a hardware model written in the Verilog hardware description language. These behavioral simulations verify that the hardware implementation matches the C model. The model was synthesized using the Synopsis synthesis tool. The gate count and clock rate of the design were estimated using the synthesis results

VLSI implementation of discrete cosine transform using a new asynchronous pipelined architecture.

Lee Chi-wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 191-196).Abstracts in English and Chinese.Abstract of this thesis entitled: --- p.i摘要 --- p.iiiAcknowledgements --- p.vTable of Contents --- p.viiList of Tables --- p.xList of Figures --- p.xiChapter Chapter1 --- Introduction --- p.1Chapter 1.1 --- Synchronous Design --- p.1Chapter 1.2 --- Asynchronous Design --- p.2Chapter 1.3 --- Discrete Cosine Transform --- p.4Chapter 1.4 --- Motivation --- p.5Chapter 1.5 --- Organization of the Thesis --- p.6Chapter Chapter2 --- Asynchronous Design Methodology --- p.7Chapter 2.1 --- Overview --- p.7Chapter 2.2 --- Background --- p.8Chapter 2.3 --- Past Designs --- p.10Chapter 2.4 --- Micropipeline --- p.12Chapter 2.5 --- New Asynchronous Architecture --- p.15Chapter Chapter3 --- DCT/IDCT Processor Design Methodology --- p.24Chapter 3.1 --- Overview --- p.24Chapter 3.2 --- Hardware Architecture --- p.25Chapter 3.3 --- DCT Algorithm --- p.26Chapter 3.4 --- Used Architecture and DCT Algorithm --- p.30Chapter 3.4.1 --- Implementation on Programmable DSP Processor --- p.31Chapter 3.4.2 --- Implementation on Dedicated Processor --- p.33Chapter Chapter4 --- New Techniques for Operating Dynamic Logic in Low Frequency --- p.36Chapter 4.1 --- Overview --- p.36Chapter 4.2 --- Background --- p.37Chapter 4.3 --- Traditional Technique --- p.39Chapter 4.4 --- New Technique - Refresh Control Circuit --- p.40Chapter 4.4.1 --- Principle --- p.41Chapter 4.4.2 --- Voltage Sensor --- p.42Chapter 4.4.3 --- Ring Oscillator --- p.43Chapter 4.4.4 --- "Counter, Latch and Comparator" --- p.46Chapter 4.4.5 --- Recalibrate Circuit --- p.47Chapter 4.4.6 --- Operation Monitoring Circuit --- p.48Chapter 4.4.7 --- Overall Circuit --- p.48Chapter Chapter5 --- DCT Implementation on Programmable DSP Processor --- p.51Chapter 5.1 --- Overview --- p.51Chapter 5.2 --- Processor Architecture --- p.52Chapter 5.2.1 --- Arithmetic Unit --- p.53Chapter 5.2.2 --- Switching Network --- p.56Chapter 5.2.3 --- FIFO Memory --- p.59Chapter 5.2.4 --- Instruction Memory --- p.60Chapter 5.3 --- Programming --- p.62Chapter 5.4 --- DCT Implementation --- p.63Chapter Chapter6 --- DCT Implementation on Dedicated DCT Processor --- p.66Chapter 6.1 --- Overview --- p.66Chapter 6.2 --- DCT Chip Architecture --- p.67Chapter 6.2.1 --- ID DCT Core --- p.68Chapter 6.2.1.1 --- Core Architecture --- p.74Chapter 6.2.1.2 --- Flow of Operation --- p.76Chapter 6.2.1.3 --- Data Replicator --- p.79Chapter 6.2.1.4 --- DCT Coefficients Memory --- p.80Chapter 6.2.2 --- Combination of IDCT to 1D DCT core --- p.82Chapter 6.2.3 --- Accuracy --- p.85Chapter 6.3 --- Transpose Memory --- p.87Chapter 6.3.1 --- Architecture --- p.89Chapter 6.3.2 --- Address Generator --- p.91Chapter 6.3.3 --- RAM Block --- p.94Chapter Chapter7 --- Results and Discussions --- p.97Chapter 7.1 --- Overview --- p.97Chapter 7.2 --- Refresh Control Circuit --- p.97Chapter 7.2.1 --- Implementation Results and Performance --- p.97Chapter 7.2.2 --- Discussion --- p.100Chapter 7.3 --- Programmable DSP Processor --- p.102Chapter 7.3.1 --- Implementation Results and Performance --- p.102Chapter 7.3.2 --- Discussion --- p.104Chapter 7.4 --- ID DCT/IDCT Core --- p.107Chapter 7.4.1 --- Simulation Results --- p.107Chapter 7.4.2 --- Measurement Results --- p.109Chapter 7.4.3 --- Discussion --- p.113Chapter 7.5 --- Transpose Memory --- p.122Chapter 7.5.1 --- Simulated Results --- p.122Chapter 7.5.2 --- Measurement Results --- p.123Chapter 7.5.3 --- Discussion --- p.126Chapter Chapter8 --- Conclusions --- p.130Appendix --- p.133Operations of switches in DCT implementation of programmable DSP processor --- p.133C Program for evaluating the error in DCT/IDCT core --- p.135Pin Assignments of the Programmable DSP Processor Chip --- p.142Pin Assignments of the 1D DCT/IDCT Core Chip --- p.144Pin Assignments of the Transpose Memory Chip --- p.147Chip microphotograph of the 1D DCT/IDCT core --- p.150Chip Microphotograph of the Transpose Memory --- p.151Measured Waveforms of 1D DCT/IDCT Chip --- p.152Measured Waveforms of Transpose Memory Chip --- p.156Schematics of Refresh Control Circuit --- p.158Schematics of Programmable DSP Processor --- p.164Schematics of 1D DCT/IDCT Core --- p.180Schematics of Transpose Memory --- p.187References --- p.191Design Libraries - CD-ROM --- p.19

Generic low power reconfigurable distributed arithmetic processor

Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronic and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. For modern systems, more energy is required to support the powerful computational capability which accords with the increasing requirements, and these requirements cause the change of standards not only in audio and video broadcasting but also in communication such as wireless connection and network protocols. Powerful flexibility and low consumption are repellent, but their combination in one system is the ultimate goal of designers. A generic domain-specific low-power reconfigurable processor for the distributed arithmetic algorithm is presented in this dissertation. This domain reconfigurable processor features high efficiency in terms of area, power and delay, which approaches the performance of an ASIC design, while retaining the flexibility of programmable platforms. The architecture not only supports typical distributed arithmetic algorithms which can be found in most still picture compression standards and video conferencing standards, but also offers implementation ability for other distributed arithmetic algorithms found in digital signal processing, telecommunication protocols and automatic control. In this processor, a simple reconfigurable low power control unit is implemented with good performance in area, power and timing. The generic characteristic of the architecture makes it applicable for any small and medium size finite state machines which can be used as control units to implement complex system behaviour and can be found in almost all engineering disciplines. Furthermore, to map target applications efficiently onto the proposed architecture, a new algorithm is introduced for searching for the best common sharing terms set and it keeps the area and power consumption of the implementation at low level. The software implementation of this algorithm is presented, which can be used not only for the proposed architecture in this dissertation but also for all the implementations with adder-based distributed arithmetic algorithms. In addition, some low power design techniques are applied in the architecture, such as unsymmetrical design style including unsymmetrical interconnection arranging, unsymmetrical PTBs selection and unsymmetrical mapping basic computing units. All these design techniques achieve extraordinary power consumption saving. It is believed that they can be extended to more low power designs and architectures. The processor presented in this dissertation can be used to implement complex, high performance distributed arithmetic algorithms for communication and image processing applications with low cost in area and power compared with the traditional methods