Reconfigurable Architecture For H.264/avc Variable Block Size Motion Estimation Based On Motion Activity And Adaptive Search Range

Motion Estimation (ME) technique plays a key role in the video coding systems to achieve high compression ratios by removing temporal redundancies among video frames. Especially in the newest H.264/AVC video coding standard, ME engine demands large amount of computational capabilities due to its support for wide range of different block sizes for a given macroblock in order to increase accuracy in finding best matching block in the previous frames. We propose scalable architecture for H.264/AVC Variable Block Size (VBS) Motion Estimation with adaptive computing capability to support various search ranges, input video resolutions, and frame rates. Hardware architecture of the proposed ME consists of scalable Sum of Absolute Difference (SAD) arrays which can perform Full Search Block Matching Algorithm (FSBMA) for smaller 4x4 blocks. It is also shown that by predicting motion activity and adaptively adjusting the Search Range (SR) on the reconfigurable hardware platform, the computational cost of ME required for inter-frame encoding in H.264/AVC video coding standard can be reduced significantly. Dynamic Partial Reconfiguration is a unique feature of Field Programmable Gate Arrays (FPGAs) that makes best use of hardware resources and power by allowing adaptive algorithm to be implemented during run-time. We exploit this feature of FPGA to implement the proposed reconfigurable architecture of ME and maximize the architectural benefits through prediction of motion activities in the video sequences ,adaptation of SR during run-time, and fractional ME refinement. The implemented ME architecture can support real time applications at a maximum frequency of 90MHz with multiple reconfigurable regions. iv When compared to reconfiguration of complete design, partial reconfiguration process results in smaller bitstream size which allows FPGA to implement different configurations at higher speed. The proposed architecture has modular structure, regular data flow, and efficient memory organization with lower memory accesses. By increasing the number of active partial reconfigurable modules from one to four, there is a 4 fold increase in data re-use. Also, by introducing adaptive SR reduction algorithm at frame level, the computational load of ME is reduced significantly with only small degradation in PSNR (≤0.1dB)

Motion estimation and video coding

Over the last ten years. research on the analysis of visual motion has come to play a key role in the fields of data compression for visual communication as well as computer vision. Enormous efforts have been made on the design of various motion estimation algorithms. One of the fundamental tasks in motion estimation is the accurate measurement of 2-D dense motion fields. For this purpose. we devise and present in this dissertation a multiattribute feedback computational framework. In this framework for each pixel in an image. instead of a single image intensity. multiple image attributes are computed as conservation information. To enhance the estimation accuracy. feedback technique is applied. Besides. the proposed algorithm needs less differentiation and thus is more robust to various noises. With these features. the estimation accuracy is improved considerably. Experiments have demonstrated that the proposed algorithm outperforms most of the existing techniques that compute 2-D dense motion fields in terms of accuracy. The estimation of 2-D block motion vector fields has been dominant among techniques in exploiting the temporal redundancy in video coding owing to its straightforward implementation and reasonable performance. But block matching is still a computational burden in real time video compression. Hence. efficient block matching techniques remain in demand. Existing block matching methods including full search and multiresolution techniques treat every region in an image domain indiscriminately no matter whether the region contains complicated motion or not. Motivated from this observation. we have developed two thresholding techniques for block matching in video coding. in which regions experiencing relatively uniform motion are withheld from further processing via thresholfing. thus saving compu­tation drastically. One is a thresholding multiresolution block matching. Extensive experiments show that the proposed algorithm has a consistent performance for sequences with different motion complexities. It reduces the processing time ranging from 14% to 20% while maintaining almost the same quality of the reconstructed image (only about 0.1 dB loss in PSNR). compared with the fastest existing multiresolution technique. The other is a thresholding hierarchical block matching where no pyramid is actually formed. Experiments indicate that for sequences with less motion such as videoconferencing sequences. this algorithm works faster and has much less motion vectors than the thresholding multiresolution block matching method