20,561 research outputs found
Emulating Digital Logic using Transputer Networks (Very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing
power, memory and communications is decided in computing systems. This will have a profound
impact on the design rules for the controlling software. In particular, the criteria for judging efficiency
of the algorithms will be somewhat different. This paper explores some of these implications through
the development of highly parallel and highly distributable algorithms based on occam and transputer
networks. The major results reported are a new simplicity for software designs, a corresponding ability
to reason (formally and informally) about their properties, the reusability of their components and some
real performance figures which demonstrate their practicality. Some guidelines to assist in these designs
are also given. As a vehicle for discussion, an interactive simulator is developed for checking the
functional and timing characteristics of digital logic circuits of arbitrary complexity
Noise-based information processing: Noise-based logic and computing: what do we have so far?
We briefly introduce noise-based logic. After describing the main motivations
we outline classical, instantaneous (squeezed and non-squeezed), continuum,
spike and random-telegraph-signal based schemes with applications such as
circuits that emulate the brain functioning and string verification via a slow
communication channel.Comment: Invited talk at the 21st International Conference on Noise and
Fluctuations, Toronto, Canada, June 12-16, 201
CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs). It is shown ternary logic has promising future in CNTFETs when compare to conventional binary logic design, due to its simplicity and energy efficiency in digital design reduced circuit overhead such as chip area and interconnection. In this research, existing CNTFET-based binary inverter and standard ternary inverter with resistive-load (STI-R) for comparison with the other three types of inverter are proposed - Complementary Standard Ternary Inverter (CSTI); Standard Ternary Inverter with 1 resistor and 3 NCNTFET (NSTI-R); Standard Ternary Inverter with 1 resistor and 3 PCNTFET (PSTI-R) to analysis the performance, structure design and application. In addition, the research covers all the basic logic Ternary NAND gate and Ternary NOR gate for further benchmarking. All simulation results using SPICE are obtained and analyzed in the Direct Current (DC) setting and verifed using half adder. Further study behavior of ternary logic includes the implementation of partial binary design into the ternary design and performance benchmarking. The result shows the CSTI have advantage on low power design with low leakage while NSTI-R has advantage on high-speed design inverter. In addition, partial binary design in the arithmetic circuit ternary design with CSTI shows added advantage in a low power design
Multiple-Valued Structures of Intellectual Systems
The basic construction concepts of many-valued intellectual systems, which are adequate to primal
problems of person activity and using hybrid tools with many-valued intellectual systems being two-place, but
simulating neuron processes of space toting which are different on a level of actions, inertial and threshold of
properties of neuron diaphragms, and also frequency modification of the following transmitted messages are
created. All enumerated properties and functions in point of fact are essential not only are discrete on time, but
also many-valued
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