A Surface Potential and Current Model for Polarity-Controllable Silicon Nanowire FETs

Silicon nanowire FET (SiNWFET) with dynamic polarity control has been experimentally demonstrated and has shown large potential in circuit applications. To fully explore its circuit-level opportunities, a physics-based compact model of the polarity-controllable SiNWFET is required. Therefore, in this paper, we extend the solution for conventional SiNWFETs to polarity-controllable SiNWFETs. By solving the current continuity equation, the potential distribution and drain current is obtained. The model shows good aoreement with TCAD simulation. It can be used as the core to develop the complete compact model for polarity-controllable SiNWFETs

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon Wnanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V-T). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V-T. This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of similar to 0.5 V between low-V-T and high-V-T configurations, while high-V-T configuration reduces the leakage current by two orders of magnitude as compared to low-V-T configuration

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Controllable-Polarity Silicon Nanowire Transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the on-line configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck-at ptype and stuck-at n-type, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck- Open. We proposed an appropriate test method to capture such faults as well

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon NanoWire FET (SiNWFET), is being introduced by the research community. These devices keep on pursuing Mooreâs Law by improving channel electrostatic controllability, thereby reducing the Off âstate leakage current. In addition to these improvements, recent developments introduced devices with enhanced capabilities, such as Controllable-Polarity (CP) SiNWFETs, which make them very interesting for compact logic cell and arithmetic circuits. At advanced technology nodes, the amount of physical controls, during the fabrication process of nanometer devices, cannot be precisely determined because of technology fluctuations. Consequently, the structural parameters of fabricated circuits can be significantly different from their nominal values. Moreover, giving an a-priori conclusion on the variability of advanced technologies for emerging nanoscale devices, is a difficult task and novel estimation methodologies are required. This is a necessity to guarantee the performance and the reliability of future integrated circuits. Statistical analysis of process variation requires a great amount of numerical data for nanoscale devices. This introduces a serious challenge for variability analysis of emerging technologies due to the lack of fast simulation models. One the one hand, the development of accurate compact models entails numerous tests and costly measurements on fabricated devices. On the other hand, Technology Computer Aided Design (TCAD) simulations, that can provide precise information about devices behavior, are too slow to timely generate large enough data set. In this research, a fast methodology for generating data set for variability analysis is introduced. This methodology combines the TCAD simulations with a learning algorithm to alleviate the time complexity of data set generation. Another formidable challenge for variability analysis of the large circuits is growing number of process variation sources. Utilizing parameterized models is becoming a necessity for chip design and verification. However, the high dimensionality of parameter space imposes a serious problem. Unfortunately, the available dimensionality reduction techniques cannot be employed for three main reasons of lack of accuracy, distribution dependency of the data points, and finally incompatibility with device and circuit simulators. We propose a novel technique of parameter selection for modeling process and performance variation. The proposed technique efficiently addresses the aforementioned problems. Appropriate testing, to capture manufacturing defects, plays an important role on the quality of integrated circuits. Compared to conventional CMOS, emerging nano-devices such as CP-SiNWFETs have different fabrication process steps. In this case, current fault models must be extended for defect detection. In this research, we extracted the possible fabrication defects, and then proposed a fault model for this technology. We also provided a couple of test methods for detecting the manufacturing defects in various types of CP-SiNWFET logic gates. Finally, we used the obtained fault model to build fault tolerant arithmetic circuits with a bunch of superior properties compared to their competitors

Interface Engineering to Control Charge Transport in Colloidal Semiconductor Nanowires and Nanocrystals

Colloidal semiconductor nanocrystals (NCs) are a class of materials that has rapidly gained prominence and has shown the potential for large area electronics. These materials can be synthesized cheaply and easily made in high quality, with tunable electronic properties. However, evaluating if colloidal nanostructures can be used as a viable semiconducting material for large area electronics and more complex integrated circuits has been a long standing question in the field. When these materials are integrated into solid-state electronics, multiple interfaces need to be carefully considered to control charge transport, these interfaces are the: metal contact/semiconductor, dielectric/semiconductor and the nanocrystal surface. Here, we use colloidal nanowire (NW) field-effect transistors (FETs) as a model system to understand doping and hysteresis. Through controllable doping, we fabricated PbSe NW inverters that exhibit amplification and demonstrate that these nanostructured materials could be used in more complex integrated circuits. By manipulating the dielectric interface, we are able to reduce the hysteresis and make low-voltage, low-hysteresis PbSe NW FETs on flexible plastic, showing the promise of colloidal nanostructures in large area flexible electronics. In collaboration, we are able to fabricate high-performance CdSe NC FETs through the use of a novel ligand, ammonium thiocyanate to enhance electronic coupling, and extrinsic atom in indium to dope and passivate surface traps, to yield mobilities exceeding 15 cm2V-1s-1. Combining high-mobility CdSe NC FETs with our low-voltage plastic platform, we were able to translate the exceptional devices performances on flexible substrates. This enables us to construct, for the first time, nanocrystal integrated circuits (NCICs) constructed from multiple well-behaved, high-performance NC-FETs. These transistors operate with small variations in device parameters over large area in concert, enabling us to fabricate NCIC inverters, amplifiers and ring oscillators. Device performance is comparable to other emerging solution-processable materials, demonstrating that this class of colloidal NCs as a viable semiconducting material for large area electronic applications

Carbon nanotube neurotransistors with ambipolar memory and learning functions

In recent years, neuromorphic computing has gained attention as a promising approach to enhance computing efficiency. Among existing approaches, neurotransistors have emerged as a particularly promising option as they accurately represent neuron structure, integrating the plasticity of synapses along with that of the neuronal membrane. An ambipolar character could offer designers more flexibility in customizing the charge flow to construct circuits of higher complexity. We propose a novel design for an ambipolar neuromorphic transistor, utilizing carbon nanotubes as the semiconducting channel and an ion-doped sol-gel as the polarizable gate dielectric. Due to its tunability and high dielectric constant, the sol-gel effectively modulates the conductivity of nanotubes, leading to efficient and controllable short-term potentiation and depression. Experimental results indicate that the proposed design achieves reliable and tunable synaptic responses with low power consumption. Our findings suggest that the method can potentially provide an efficient solution for realizing more adaptable cognitive computing systems.Comment: 16 pages, 6 pages of supporting information at the end, 6 main figures, 10 supporting figure

Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing

Silicon Nanowires (SiNWs) are considered the fundamental component blocks of future nanoelectronics. Many interesting properties have gained them such a prominent position in the investigation in recent decades. Large surface-to-volume ratio, bio-compatibility, band-gap tuning are among the most appealing features of SiNWs. More importantly, in the ongoing process of dimension miniaturization, SiNWs compatibility with the existing and reliable silicon technology stands as a fundamental advantage. Consequently, the employment of SiNWs spred in several application fields: from computational logic where SiNWs are used to realize transistors, to bio-chemical sensing and nanophotonic applications. In this thesis work we concentrate our attention on the employment of SiNWs in computational logic and bio-chemical sensing. In particular, we aim at giving a contribution in the modelling and simulation of SiNW-based electron devices. Given the current intense investigation of new devices, the modelling of their electrical behaviour is strongly required. On one side, modelling procedures could give an insight on the physical phenomena of transport in nanometer scale systems where quantum effects are dominant. On the other side, the availability of compact models for actual devices can be of undeniable help in the future design process. This work is divided into two parts. After a brief introduction on Silicon Nanowires, the main fabrication techniques and their properties, the first part is dedicated to the modelling of Multiple-Independent Gate Transistors, a new generation of devices arisen from the composition of Gate-All-Around Transistors, finFETs and Double-Gate Transistors. Interesting applications resulting from their employment are Vertically-stacked Silicon Nanowire FETs, known to have an ambipolar behaviour, and Silicon Nanowire Arrays. We will present a compact numerical model for composite Multiple-Independent Gate Transistors which allows to compute current and voltages in complex structures. Validation of the model through simulation proves the accuracy and the computational efficiency of the resulting model. The second part of the thesis work is instead devoted to Silicon Nanowires for bio-chemical sensing. In this respect, major attention is given to Porous Silicon (PS), a non-crystalline material which demonstrated peculiar features apt for sensing. Given its not regular microscopic morphology made of a complex network of crystalline and non-crystalline regions, PS has large surface-to-volume ratio and a relevant chemical reactivity at room temperature. In this work we start from the fabrication of PS nanowires at Istituto Nazionale di Ricerca Metrologica in Torino (I.N.Ri.M.) to devise two main models for PSNWs which can be used to understand the effects of porosity on electron transport in these structures. The two modelling procedures have different validity regimes and efficiently take into account quantum effects. Their description and results are presented. The last part of the thesis is devoted to the impact of surface interaction of molecular compounds and dielectric materials on the transport properties of SiNWs. Knowing how molecules interact with silicon atoms and how the conductance of the wire is affected is indeed the core of SiNWs used for bio-chemical sensing. In order to study the phenomena involved, we performed ab-initio simulations of silicon surface interacting with SO2 and NO2 via the SIESTA package, implementing DFT code. The calculations were performed at Institut de Ciencia De Materials de Barcelona (ICMAB-CSIC) using their computational resources. The results of this simulation step are then exploited to perform simulation of systems made of an enormous quantity of atoms. Due to their large dimensions, atomistic simulations are not affordable and other approaches are necessary. Consequently, calculations with physics-based softwares on a larger spatial scale were adopted. The description of the obtained results occupies the last part of the work together with the discussion of the main theoretical insight gained with the conducted study

Intracellular Recordings of Action Potentials by an Extracellular Nanoscale Field-Effect Transistor

The ability to make electrical measurements inside cells has led to many important advances in electrophysiology. The patch clamp technique, in which a glass micropipette filled with electrolyte is inserted into a cell, offers both high signal-to-noise ratio and temporal resolution. Ideally, the micropipette should be as small as possible to increase the spatial resolution and reduce the invasiveness of the measurement, but the overall performance of the technique depends on the impedance of the interface between the micropipette and the cell interior, which limits how small the micropipette can be. Techniques that involve inserting metal or carbon microelectrodes into cells are subject to similar constraints. Field-effect transistors (FETs) can also record electric potentials inside cells, and because their performance does not depend on impedance, they can be made much smaller than micropipettes and microelectrodes. Moreover, FET arrays are better suited for multiplexed measurements. Previously, we have demonstrated FET-based intracellular recording with kinked nanowire structures, but the kink configuration and device design places limits on the probe size and the potential for multiplexing. Here, we report a new approach in which a $SiO_2$ nanotube is synthetically integrated on top of a nanoscale FET. This nanotube penetrates the cell membrane, bringing the cell cytosol into contact with the FET, which is then able to record the intracellular transmembrane potential. Simulations show that the bandwidth of this branched intracellular nanotube FET (BIT-FET) is high enough for it to record fast action potentials even when the nanotube diameter is decreased to 3 nm, a length scale well below that accessible with other methods. Studies of cardiomyocyte cells demonstrate that when phospholipid-modified BIT-FETs are brought close to cells, the nanotubes can spontaneously penetrate the cell membrane to allow the full-amplitude intracellular action potential to be recorded, thus showing that a stable and tight seal forms between the nanotube and cell membrane. We also show that multiple BIT-FETs can record multiplexed intracellular signals from both single cells and networks of cells.Chemistry and Chemical BiologyEngineering and Applied SciencesPhysic