A PLL based built-in self-test for MEMS sensors

A new readout circuit for capacitive Micro-Electrical-Mechanical System (MEMS) devices has been proposed, developed and simulated in this thesis. The readout circuit utilizes a Phase Locked Loop (PLL) to convert variations of MEM capacitance to time domain signals. The proposed circuit demonstrates a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Post layout simulation results in Cadence environment using TSMC CMOS 65nm technology indicate that the implemented readout circuit can successfully measure and detect minor variations of MEMS capacitance from its nominal value