On the production testing of analog and digital circuits

This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I scalar circuits, Biquadratic filters and many other applications. This circuit is often used to implement voltage followers, current followers and voltage to current converters. Five faults are assumed per transistor. It is shown that, to obtain 100% fault coverage, the CCII has to be operated in voltage to current converter mode. Only two test values are required to obtain this fault coverage. Additionally, the thesis focuses on the production testing of Memristor Ratioed Logic (MRL) gates because this was not studied before. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that in order to obtain full coverage for the MRL NAND and NOR gates, two solutions are proposed. The first is the usage of scaled input voltages to prevent the output from falling in the undefined region. The second proposed solution is changing the switching threshold VM of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the 100% coverage test set in the conventional NAND and NOR CMOS designs

Chemical Current-Conveyor: a new approach in biochemical computation

Biochemical sensors that are low cost, small in size and compatible with integrated circuit technology play an essential part in the drive towards personalised healthcare and the research described in this thesis is concerned with this area of medical instrumentation. A new biochemical measurement system able to sense key properties of biochemical fluids is presented. This new integrated circuit biochemical sensor, called the Chemical Current-Conveyor, uses the ion sensitive field effect transistor as the input sensor combined with the current-conveyor, an analog building-block, to produce a range of measurement systems. The concept of the Chemical Current-Conveyor is presented together with the design and subsequent fabrication of a demonstrator integrated circuit built on conventional 0.35μm CMOS silicon technology. The silicon area of the Chemical Current-Conveyor is (92μm x 172μm) for the N-channel version and (99μm x 165μm) for the P-channel version. Power consumption for the N-channel version is 30μW and 43μW for the P-channel version with a full load of 1MΩ. The maximum sensitivity achieved for pH measurement was 46mV per pH. The potential of the Chemical Current Conveyor as a versatile biochemical integrated circuit, able to produce output information in an appropriate form for direct clinical use has been confirmed by applications including measurement of (i) pH, (ii) buffer index ( ), (iii) urea, (iv) creatinine and (v) urea:creatinine ratio. In all five cases the device has been demonstrated successfully, confirming the validity of the original aim of this research project, namely to produce a versatile and flexible analog circuit for many biochemical measurement applications. Finally, the thesis closes with discussion of another potential application area for the Chemical Current Conveyor and the main contributions can be summarised by the design and development of the first: ISFET based current-conveyor biochemical sensor, called 'Chemical Current Conveyor, CCCII+' has been designed and developed. It is a general purpose biochemical analog building-block for several biochemical measurements. Real-time buffer capacity measurement system, based on the CCCII+, which exploits the imbedded analog computation capability of the CCCII+. Real-time enzyme based CCCII+ namely, Creatinine-CCCII+ and Urea-CCCII+ for real-time monitoring system of renal system. The system can provide outputs of 3 important parameters of the renal system, namely (i) urea concentration, (ii) creatinine concentration, and (ii) urea to creatinine ratio

Memcapacitor and Meminductor Circuit Emulators: A Review

This research was funded by the Japanese KAKENHI through Grant Number JP18k04275 and Spanish Ministry of Education, Culture, and Sport (MECD), through Project TEC2017-89955-P and Grant Numbers: FPU16/01451 and FPU16/04043.In 1971, Prof. L. Chua theoretically introduced a new circuit element, which exhibited a different behavior from that displayed by any of the three known passive elements: the resistor, the capacitor or the inductor. This element was called memristor, since its behavior corresponded to a resistor with memory. Four decades later, the concept of mem-elements was extended to the other two circuit elements by the definition of the constitutive equations of both memcapacitors and meminductors. Since then, the non-linear and non-volatile properties of these devices have attracted the interest of many researches trying to develop a wide range of applications. However, the lack of solid-state implementations of memcapacitors and meminductors make it necessary to rely on circuit emulators for the use and investigation of these elements in practical implementations. On this basis, this review gathers the current main alternatives presented in the literature for the emulation of both memcapacitors and meminductors. Different circuit emulators have been thoroughly analyzed and compared in detail, providing a wide range of approaches that could be considered for the implementation of these devices in future designs.Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT) Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research (KAKENHI) JP18k04275Spanish Ministry of Education, Culture, and Sport (MECD) TEC2017-89955-P FPU16/01451 FPU16/0404

Synthesis and monolithic integration of analogue signal processing networks

Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands. One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges. Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically. Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported. This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.Square Kilometer Array (SKA) project - postgraduate scholarshipElectrical, Electronic and Computer EngineeringPhDUnrestricte

Design of Building Blocks for Trit Algorithm

This thesis attempts to design the building blocks for TRIT algorithm. PSPICE was used for simulation. The building blocks were laidout in Magic.Electrical Engineerin

Current–Mode Fractional–Order Electronically Controllable Integrator Design

This contribution presents a design of a current–mode fractional–order electronically controllable integrator which can be used as a building block for a design of fractional–order (FO) circuits. The design is based on a 2nd–order Follow–the–Leader–Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th–order FLF topology

Investigation of Current Sensing Using Inherent Resistance

A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named “IRS” here, and it stands for Inherent Resistance Current Sensing. To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area. It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor. In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them. Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided

Current Conveyor All-Pass Sections: Brief Review and Novel Solution

This study relates to the review of an important analog electronic function in form of all-pass filter’s realization using assorted current conveyor types and their relative performances, which resulted in a novel solution based on a new proposed active element. The study encompasses notable proposals during last the decade or more, and provides a platform for a broader future survey on the topic for enhancing the knowledge penetration amongst the researchers in the specified field. A new active element named EXCCII (Extra-X second generation current conveyor) with buffered output is found in the study along with its use in a new first-order all-pass section, with possible realization using commercially available IC (AD-844) and results