Animated computer graphics models of space and earth sciences data generated via the massively parallel processor

The capability was developed of rapidly producing visual representations of large, complex, multi-dimensional space and earth sciences data sets via the implementation of computer graphics modeling techniques on the Massively Parallel Processor (MPP) by employing techniques recently developed for typically non-scientific applications. Such capabilities can provide a new and valuable tool for the understanding of complex scientific data, and a new application of parallel computing via the MPP. A prototype system with such capabilities was developed and integrated into the National Space Science Data Center's (NSSDC) Pilot Climate Data System (PCDS) data-independent environment for computer graphics data display to provide easy access to users. While developing these capabilities, several problems had to be solved independently of the actual use of the MPP, all of which are outlined

METAPHOR: Programmer's guide, Version 1

The internal structure of the Michigan Evaluation Aid for Perphormability (METAPHOR), an interactive software package to facilitate performability modeling and evaluation is described. Revised supplemented guides are prepared in order to maintain an up-to-date documentation of the system. Programmed tools to facilitate each step of performability model construction and model solution are given

IEEE Wireless LAN capacity in multicell environments with rate adaptation

Since the advent of the first IEEE 802.11 standard, many research efforts have been spent on evaluating different aspects of the specification. In this paper, we present a new method to predict the capacity of a multicell IEEE 802.11 network. The mechanism takes the effect of co-channel and adjacent channel interference into account. In addition, the study of a common rate adaptation algorithm is included. When the effect of rate adaptation is considered within the throughput computation, the results provided by our algorithm are closer to the measurements obtained in a real scenario. To the best of our knowledge, this paper presents the first analytical study of throughput performance including both types of interferences and the effect of bit rate adaptatio

Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 4: FTMP executive summary

The FTMP architecture is a high reliability computer concept modeled after a homogeneous multiprocessor architecture. Elements of the FTMP are operated in tight synchronism with one another and hardware fault-detection and fault-masking is provided which is transparent to the software. Operating system design and user software design is thus greatly simplified. Performance of the FTMP is also comparable to that of a simplex equivalent due to the efficiency of fault handling hardware. The FTMP project constructed an engineering module of the FTMP, programmed the machine and extensively tested the architecture through fault injection and other stress testing. This testing confirmed the soundness of the FTMP concepts

Can Parallel Algorithms Enhance Serial Implementation?

Consider the serial emulation of a parallel algorithm. The thesis presented in this paper is rather broad. It suggests that such a serial emulation has the potential advantage of running on a serial machine faster than a standard serial algorithm for the same problem. The main concrete observation is very simple: just before the serial emulation of a round of the parallel algorithm begins, the whole list of memory addresses needed during this round is readily available; and, we can start fetching all these addresses from secondary memories at this time. This permits prefetching the data that will be needed in the next "time window", perhaps by means of pipelining; these data will then be ready at the fast memories when requested by the CPU. The possibility of distributing memory addresses (or memory fetch units) at random over memory modules, as has been proposed in the context of implementing the parallel-random-access machine (PRAM) design space, is discussed. This work also suggests that a multi-stage effort to build a parallel machine may start with "parallel memories" and serial processing, deferring parallel processing to a later stage. The general approach has the following advantage: a user-friendly parallel programming language can be used already in its first stage. This is in contrast to a practice of compromising user-friendliness of parallel computer interfaces (i.e., parallel programming languages), and may offer a way for alleviating a so-called "parallel software crisis". It is too early to reach conclusions regarding the significance of the thesis of this paper. Preliminary experimental results with respect to the fundamental and practical problem of constructing suffix trees indicate that drastic improvements in running time might be possible. Serious attempts to follow it up are needed to determine its usefulness. Parts of this paper are intentionally written in an informal way, suppressing issues that will have to be resolved in the context of a concrete implementation. The intention is to stimulate debate and provoke suggestions and other specific approaches. Validity of our thesis would imply that a standard computer science curriculum, which prepares young graduates for a professional career of over forty years, will have to include the topic of parallel algorithms irrespective of whether (or when) parallel processing will succeed serial processing in the general purpose computing market. (Also cross-referenced as UMIACS-TR-91-145.1

FINDS: A fault inferring nonlinear detection system programmers manual, version 3.0

Detailed software documentation of the digital computer program FINDS (Fault Inferring Nonlinear Detection System) Version 3.0 is provided. FINDS is a highly modular and extensible computer program designed to monitor and detect sensor failures, while at the same time providing reliable state estimates. In this version of the program the FINDS methodology is used to detect, isolate, and compensate for failures in simulated avionics sensors used by the Advanced Transport Operating Systems (ATOPS) Transport System Research Vehicle (TSRV) in a Microwave Landing System (MLS) environment. It is intended that this report serve as a programmers guide to aid in the maintenance, modification, and revision of the FINDS software

Intelligent Tutoring System: Teaching Children to Write Alphabets

Teaching a children to write alphabets can be a hassle for parents and teachers especially at the kindergarten because of some factors such as time management, large class etc. The traditional way by using the alphabets book are proven to be effective but how to expose the early age children about computer as a first thing to learn? The paper begins with background discussion on problem statement of the project; scope of the study will be focusing on alphabets drawing and programming with Artificial Intelligence (AI). Following that, further explanation on the research project including features of product to be developed, tools required is being presented. For this project, there would be two main activities to take place in shape of research and prototyping for final product for this project. The questionnaire and observation studies are obtained in order to get the full ideas of the proposed system. Details on project works can be found in methodology section of this report. This report is wrapped up with a literature review to present the idea of the importance of AI in Intelligent Tutoring System (ITS)

NASTRAN interfacing modules within the Integrated Analysis Capability (IAC) Program

The IAC program provides the framework required for the development of an extensive multidisciplinary analysis capability. Several NASTRAN related capabilities were developed which can all be expanded in a routine manner to meet in-house unique needs. Plans are to complete the work discussed herein and to provide it to the engineering community through COSMIC. Release is to be after the current IAC Level 2 contract work on the IAC executive system is completed and meshed with the interfacing modules and analysis capabilities under development at the GSFC