Design and Implementation of FPGA-Based Multi-Rate BPSK- QPSK Modem with Focus on Carrier Recovery and Time Synchronization

Regarding the high performance and reconfigurability of Field Programmable Gate Arrays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. Therefore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmitter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems considering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effectiveness of the implemented transceiver has been evaluated based on its ability to deal with the carrier and symbol rate frequency offsets. The introduced platform shows promising results in its capability to resolve up to ±200 kHz carrier frequency offset and ±14 kHz symbol rate frequency offset (in 18 dB SNR). Furthermore, on the basis of the performed assessment, it is concluded that the introduced model is robust and potential to be applied in array-based or multi-channel networks