Phase ambiguity resolution for offset QPSK modulation systems

A demodulator for Offset Quaternary Phase Shift Keyed (OQPSK) signals modulated with two words resolves eight possible combinations of phase ambiguity which may produce data error by first processing received I(sub R) and Q(sub R) data in an integrated carrier loop/symbol synchronizer using a digital Costas loop with matched filters for correcting four of eight possible phase lock errors, and then the remaining four using a phase ambiguity resolver which detects the words to not only reverse the received I(sub R) and Q(sub R) data channels, but to also invert (complement) the I(sub R) and/or Q(sub R) data, or to at least complement the I(sub R) and Q(sub R) data for systems using nontransparent codes that do not have rotation direction ambiguity

A small terminal for satellite communication systems

A small portable, low-cost satellite communications terminal system incorporating a modulator/demodulator and convolutional-Viterbi coder/decoder is described. Advances in signal processing and error-correction techniques in combination with higher power and higher frequencies aboard satellites allow for more efficient use of the space segment. This makes it possible to design small economical earth stations. The Advanced Communications Technology Satellite (ACTS) was chosen to test the system. ACTS, operating at the Ka band incorporates higher power, higher frequency, frequency and spatial reuse using spot beams and polarization

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions

NASA. Lewis Research Center Advanced Modulation and Coding Project: Introduction and overview

The Advanced Modulation and Coding Project at LeRC is sponsored by the Office of Space Science and Applications, Communications Division, Code EC, at NASA Headquarters and conducted by the Digital Systems Technology Branch of the Space Electronics Division. Advanced Modulation and Coding is one of three focused technology development projects within the branch's overall Processing and Switching Program. The program consists of industry contracts for developing proof-of-concept (POC) and demonstration model hardware, university grants for analyzing advanced techniques, and in-house integration and testing of performance verification and systems evaluation. The Advanced Modulation and Coding Project is broken into five elements: (1) bandwidth- and power-efficient modems; (2) high-speed codecs; (3) digital modems; (4) multichannel demodulators; and (5) very high-data-rate modems. At least one contract and one grant were awarded for each element

Design Of Multi-Modulation Baseband Modulator And Demodulator For Software Defined Radio

In contrast to hardware-based radio that only delivers single communication service using particular standard, the software defined radio (SDR) provides a highly reconfigurable platform to integrate various functions for multi-modulation, multiband and multi-standard wireless communication systems. However, this project is only based on multi-modulation SDR, such as 4-PAM, BPSK, QPSK and 16-QAM.The configurable multi-modulation baseband modulator (MMBM) and demodulator (MMBD) are designed using digital signal processing (DSP) algorithms based on common features shared by single-modulation structures, and then implemented into Xilinx Virtex-4 FPGA. Comparing the real-time and simulation results shows that the timings are equivalent, and the sign and magnitude changes are significant

RapidRadio: A Domain-Specific Productivity Enhancing Framework

The RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity enhancing tool that reduces the required knowledge-base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. The architecture of the receiver deployed by the framework and its implementation are discussed. The framework's capacity to classify a signal and deploy a functional receiver is validated with over-the-air experiments

Multichannel demultiplexer-demodulator

One of the critical satellite technologies in a meshed VSAT (very small aperture terminal) satellite communication networks utilizing FDMA (frequency division multiple access) uplinks is a multichannel demultiplexer/demodulator (MCDD). TRW Electronic Systems Group developed a proof-of-concept (POC) MCDD using advanced digital technologies. This POC model demonstrates the capability of demultiplexing and demodulating multiple low to medium data rate FDMA uplinks with potential for expansion to demultiplexing and demodulating hundreds to thousands of narrowband uplinks. The TRW approach uses baseband sampling followed by successive wideband and narrowband channelizers with each channelizer feeding into a multirate, time-shared demodulator. A full-scale MCDD would consist of an 8 bit A/D sampling at 92.16 MHz, four wideband channelizers capable of demultiplexing eight wideband channels, thirty-two narrowband channelizers capable of demultiplexing one wideband signal into 32 narrowband channels, and thirty-two multirate demodulators. The POC model consists of an 8 bit A/D sampling at 23.04 MHz, one wideband channelizer, 16 narrowband channelizers, and three multirate demodulators. The implementation loss of the wideband and narrowband channels is 0.3dB and 0.75dB at 10(exp -7) E(sub b)/N(sub o) respectively

A Non-Destructive Evaluation Application Using Software Defined Radios and Bandwidth Expansion

The development of low-complexity, lightweight and low-cost Non-Destructive Evaluation (NDE) equipment for microwave device testing is desirable from a maintenance efficiency and operational availability perspective. Current NDE equipment tends to be custom-designed, cumbersome and expensive. Software Defined Radio (SDR) technology, and a bandwidth expansion technique that exploits a priori transmit signal knowledge and auto-correlation provides a solution. This research investigated the reconstruction of simultaneous SDR receiver instantaneous bandwidth (sub-band) collections using single, dual and multiple SDR receivers. The adjacent sub-bands, collectively spanning a transmit signal bandwidth were auto-correlated with a replica transmit signal to restore frequency and phase offsets. The offsets arise due to different local oscillator manufacturing tolerances, temperature effects and ageing. A 100 MHz bandwidth uniform white noise signal was reconstructed from both dual (2 fi 50 MHz) and multiple (4 fi 25 MHz) SDR collections. The 100 MHz bandwidth exceeds a B205 SDR receiver instantaneous bandwidth. The auto-correlation technique minimizes SDR hardware numbers as bandwidth overlap is not required. Hardware test Symbol Error Rate (SER) was compared with a theoretical coherently detected M-ary orthogonal signal. A 2 MHz dual SDR uniform white noise signal reconstruction exhibited a 5 dBW loss when compared with the theoretical value. The 4 MHz multiple SDR signal reconstruction exhibited a 6 dBW loss. Finally, a linear feedback shift register was used to generate the uniform white noise signal. This provided near true-noise characteristics employing a polynomial primitive to ensure 236 - 1 non-repeatable sequences

Design and Implementation of FPGA-Based Multi-Rate BPSK- QPSK Modem with Focus on Carrier Recovery and Time Synchronization

Regarding the high performance and reconfigurability of Field Programmable Gate Arrays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. Therefore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmitter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems considering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effectiveness of the implemented transceiver has been evaluated based on its ability to deal with the carrier and symbol rate frequency offsets. The introduced platform shows promising results in its capability to resolve up to ±200 kHz carrier frequency offset and ±14 kHz symbol rate frequency offset (in 18 dB SNR). Furthermore, on the basis of the performed assessment, it is concluded that the introduced model is robust and potential to be applied in array-based or multi-channel networks