Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

Amplifier performance enhancement methods using positive feedback techniques

The dramatic growth in the hi-tech sector of consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication and entertainment systems including high speed cable and DSL modems, broadband wired and wireless systems, and high definition visual products require very fast and high accuracy amplifiers, data converters and filters. Analog design in the new digital CMOS submicron processes is becoming an economical necessity in the industry. The task of building fast Op-Amp with very high DC-gain is already a very difficult problem, and this task has become more difficult using these new submicron digital processes, where traditional gain enhancement techniques are loosing their ability to deliver amplifiers with sufficient gain. In this work three new methods of implementing the internal positive-feedback to build very high DC-gain amplifiers with very low gain sensitivity to signal swings are presented. Amplifiers proposed in the first method have very high current-controlled gain. A DC gain larger than 100dB is possible without limiting the speed of the amplifier. Amplifiers proposed in the second method exhibit both enhanced speed, i.e., unity gain frequency, and enhanced gain. Amplifiers proposed in the third method have self-adjusting gain without extra control block. An implementation of a 3 bit multiplying DAC in a 9-bit 165MS/s pipeline ADC built in a 1.8V, 0.21mu digital CMOS process using one of the proposed amplifiers is described. Test results show high gain with very fast settling

Slew-rate enhancement and trojan state avoiding for fully-differential operational amplifier

Operational amplifiers are fundamental building blocks in modern analog and mixed-signal systems such as data converters, switched-capacitor circuits, and filters. The fully-differential structure is extensively used in these applications because of its improved dynamic performance with respect to such aspects as signal-to-noise ratio (SNR) and total harmonic distortion (THD) when compared to its single-ended counterpart. In some of these applications, the fully-differential amplifier is required to have fast transient settling time without slew-rate limitations. Power consumption also must be taken into consideration because low power consumption can significantly reduce a battery\u27s weight and size, and extend its life-time. A Class A amplifier is a difficult configuration in which to conciliate all these requirements, since its fixed bias current can limit its maximum output current. To simultaneously meet both slew-rate and power consumption requirements, several slew-rate enhancement (SRE) techniques have been proposed in the literature, but all of them are either incompatible with the low voltage operation or exhibit either degradation in linearity or increase in circuit complexity. This thesis presents a simple SRE technique, efficient in both power and area usage, improve the slew rate while overcoming the drawbacks of state-of-the-art SRE techniques. In this work, several existing SRE techniques are discussed, and their advantages and disadvantages are identified. The proposed SRE technique is based on excess transient detection and feedback. A transient signal can be detected at the internal nodes of amplifier. Once the detected transient signal is found to be larger than a pre-defined turn-on value, the excess transient signal can be instantaneously amplified to turn on a dynamic current source and feed it back to the amplifier for current boosting. This pre-defined turn-on voltage results in a SRE circuit being solidly off during quiescent state. Small-signal performance and linearity of the original amplifier can be thus well preserved. Thanks to this excess transient feedback concept, the implementation is much simpler than that of previously reported methods, and the static power overhead is also very small. Using the proposed SRE method, a fully-differential folded-cascode two-stage op-amp has been designed and fabricated using IBM 130nm process. This amplifier is designed to validate the proposed method of improving an amplifier\u27s input-stage slew-rate. If the tail current doubles during slewing, the simulation result indicates that, at all corners, with temperature from 0°C to 60°C the average slew-rate can be enhanced by a factor of 2.6 and the 1% settling time after a large input step is reduced by 30% compared to the vales without using SRE. Any further increment in the tail transient current can further increase the internal slew rate and eventually make it equal to the output-stage slew-rate. It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to a problem of multiple operating points; this is also known as the start-up problem. An op-amp can suffer from the same problem when performance enhancement feedback is being used. In particular, a slew rate enhancement circuit (SRE) can be used to provide performance enhancement in low-power high-speed op-amp design. For such circuits, a systematic method for detecting and removal of Trojan states is presented. Using a design example and simulation results, it is demonstrated that the proposed method can effectively remove a Trojan state in an op-amp without degrading the improved slew-rate

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

A CMOS low pass filter for soc lock-in-based measurement devices

This paper presents a fully integrated Gm–C low pass ¿lter (LPF) based on a current ¿steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2 /pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature