2 research outputs found
Algoritmo de estimação de movimento e sua arquitetura de hardware para HEVC
Doutoramento em Engenharia EletrotécnicaVideo coding has been used in applications like video surveillance, video
conferencing, video streaming, video broadcasting and video storage. In a
typical video coding standard, many algorithms are combined to compress a
video. However, one of those algorithms, the motion estimation is the most
complex task. Hence, it is necessary to implement this task in real time by
using appropriate VLSI architectures. This thesis proposes a new fast motion
estimation algorithm and its implementation in real time. The results show that
the proposed algorithm and its motion estimation hardware architecture out
performs the state of the art. The proposed architecture operates at a
maximum operating frequency of 241.6 MHz and is able to process
1080p@60Hz with all possible variables block sizes specified in HEVC
standard as well as with motion vector search range of up to ±64 pixels.A codificação de vídeo tem sido usada em aplicações tais como, vídeovigilância,
vídeo-conferência, video streaming e armazenamento de vídeo.
Numa norma de codificação de vídeo, diversos algoritmos são combinados
para comprimir o vídeo. Contudo, um desses algoritmos, a estimação de
movimento é a tarefa mais complexa. Por isso, é necessário implementar esta
tarefa em tempo real usando arquiteturas de hardware apropriadas. Esta tese
propõe um algoritmo de estimação de movimento rápido bem como a sua
implementação em tempo real. Os resultados mostram que o algoritmo e a
arquitetura de hardware propostos têm melhor desempenho que os existentes.
A arquitetura proposta opera a uma frequência máxima de 241.6 MHz e é
capaz de processar imagens de resolução 1080p@60Hz, com todos os
tamanhos de blocos especificados na norma HEVC, bem como um domínio de
pesquisa de vetores de movimento até ±64 pixels
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Error control strategies in H.265|HEVC video transmission
This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University LondonWith the rapid development in video coding technologies in the last decade, high-resolution video delivery suffers from packet loss due to unreliable transmission channels (time-varying characteristics). The error Resilience approaches at channel coding level are less efficient to implement in real time video transmission as the encoded video samples are in variable code length. Therefore, error resilience in video coding standard plays a vital role to reduce the effect of error propagation and improve the perceived visual quality. The main work in this thesis is to develop an efficient error resilience mechanism for H.265|HEVC video coding standard to reduce the effects of error propagation in error-prone conditions. In this thesis, two error resilience algorithms are proposed. The first one is Adaptive Slice Encoding (ASE) error resilience algorithm. The concept of this algorithm is to extract and protect the most active slices in the coded bitstream based on the adaptive search window. This algorithm can be applied in low delay video transmission with and without using a feedback channel. It is also designed to be compatible with reference coding software manual (HM16) for H.265|HEVC coding standard. The second proposed algorithm is a joint encoder-decoder error resilience called Error resilience based on Supplemental Enhancement Information (ERSEI) algorithm. A feedback message status is used from the decoder to notify the encoder to start encoding clean random-access picture adaptively based on the decoded picture hash message status from the decoder. At the same time, the decoder will be notified to start the error concealment process whilst waiting to receive correct video data. A recovery point message from the decoder feedback channel is used to update the encoder with error messages.
In this thesis, extensive experimental work, evaluation, and comparison with state-of-the-art related algorithms have been conducted to evaluate the proposed algorithms. Furthermore, the best trade-off between the coding efficiency of the proposed error resilience algorithms and error resilience performance has been considered at the design stage. The experimental work evaluation includes both encoding conditions, i.e. error-free and error-prone. The results achieved from the experiments show significant improvements, in (Y-PSNR) results and subjective quality of the decoded bitstream, using the proposed algorithm in error-prone conditions with a variety of packet loss rates.
Moreover, experimental work is conducted to test the algorithms complexity in terms of required processing execution time at both encoding and decoding stages. Additionally, the video coding standard performance for both H.264|AVC and H.265|HEVC coding standards are evaluated in error-free and error-prone environments.
For ASE algorithm and when compared with improved region of interest (IROI) and region of interest (ROI) algorithms, a significant improvement in visual quality was the most obvious finding from the obtained results with PLRs of 2-18 (%).
For ERSEI algorithm and when compared with the default HM16 with pixel copy concealment and motion compensated error concealment (MCEC) techniques, the evaluation results indicate clear visual quality enhancement under different packet loss rates PLRs (1,2 6, 8) %.The Ministry of Higher Education and Scientific Research in Ira