Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.Texas Instruments Incorporate

Efficient FPGA Implementation of a CTC Turbo Decoder for WiMAX/LTE Mobile Systems

This chapter describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP long-term evolution (LTE) standard, respectively, for IEEE 802.16-based WiMAX systems. We initially present the serial decoding architectures for the two systems. The same approach is used; although for WiMAX the scheme implements a duo-binary code, while for LTE a binary code is included. The proposed LTE serial decoding scheme is adapted for parallel transformation. Then, considering the LTE high throughput requirements, a parallel decoding solution is proposed. Considering a parallelization with N = 2p levels, the parallel approach reduces the decoding latency N times versus the serial decoding one. For parallel approach the decoding performance suffers a small degradation, but we propose a solution that almost eliminates this degradation, by performing an overlapped data block split. Moreover, considering the native properties of the LTE quadratic permutation polynomial (QPP) interleaver, we propose a simplified parallel decoder architecture. The novelty of this scheme is that only one interleaver module is used, no matter the value of N, by introducing an even-odd merge sorting network. We propose for it a recursive approach that uses only comparators and subtractors

Pruned Bit-Reversal Permutations: Mathematical Characterization, Fast Algorithms and Architectures

A mathematical characterization of serially-pruned permutations (SPPs) employed in variable-length permuters and their associated fast pruning algorithms and architectures are proposed. Permuters are used in many signal processing systems for shuffling data and in communication systems as an adjunct to coding for error correction. Typically only a small set of discrete permuter lengths are supported. Serial pruning is a simple technique to alter the length of a permutation to support a wider range of lengths, but results in a serial processing bottleneck. In this paper, parallelizing SPPs is formulated in terms of recursively computing sums involving integer floor and related functions using integer operations, in a fashion analogous to evaluating Dedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) is presented, and closed-form expressions for BRP statistics are derived. It is shown that BRP sequences have weak correlation properties. A new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers is proposed. Using this statistic, a recursive algorithm that computes the minimum inliers count of a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers, as well as applications to pruned fast Fourier transforms and LTE turbo interleavers, are also presented. Moreover, hardware-efficient architectures for the proposed algorithms are developed. Simulation results demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.Comment: 31 page

20 years of turbo coding and energy-aware design guidelines for energy-constrained wireless applications

During the last two decades, wireless communication has been revolutionized by near-capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit error ratio (BER) than their predecessors, without requiring an increased transmission energy consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, wireless local area network, and broadcast systems. Recently, however, TCs have also been considered for energy-constrained wireless communication applications, such as wireless sensor networks and the `Internet of Things.' In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities, and hence, the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the radio frequency bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder application-specific integrated circuit (ASIC) architecture designs are exemplified, and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC

VLSI ARCHITECTURE FOR AN AREA-EFFICIENT COMPUTATION IN LTE TURBO DECODERS

Long Term Evaluation (LTE) has been used to achieve peak data rates in wireless communication system. Turbo codes are used as the channel encoding scheme. MAP algorithm has been used as a decoding scheme. Complexity in MAP algorithm is reduced by implementing the algorithm in log domain giving rise to Log MAP algorithm. The main objective of this work is to reduce the complexity of state metric computation by employing of various algorithms and these algorithms differ only by their implementation of correction terms. The ACS unit is implemented using constant log MAP algorithm, linear log MAP algorithm, MAX log MAP algorithm, multi step log MAP algorithm and hybrid log MAP algorithm. The state metric calculation is implemented with the help of radix-4 Add -Compare-Select (ACS) unit. The distance calculation involved between two concurrent computations of state metric can be shared among them which give rise to Maximum Shared Resource (MSR) architecture. The proposed implementation of these algorithms leads to reduction in the power dissipation, propagation delay and the number of logical elements used for the recursion computation in turbo decoders used in LTE system. The MSR architecture for recursion computation reduces the number of LUTs by 12.1% when compared with the existing

Extrinsic information transfer charts for characterizing the iterative decoding convergence of fully parallel turbo decoders

Fully parallel turbo decoders (FPTDs) have been shown to offer a more-than-sixfold processing throughput and latency improvement over the conventional logarithmic Bahl–Cocke–Jelinek–Raviv (Log-BCJR) turbo decoders. Rather than requiring hundreds or even thousands of time periods to decode each frame, such as the conventional Log-BCJR turbo decoders, the FPTD completes each decoding iteration using only one or two time periods, although up to six times as many decoding iterations are required to achieve the same error correction performance. Until now, it has not been possible to explain this increased iteration requirement using an extrinsic information transfer (EXIT) chart analysis, since the two component decoders are not alternately operated in the FPTD. Hence, in this paper, we propose a novel EXIT chart technique for characterizing the iterative exchange of not only extrinsic logarithmic likelihood ratios in the FPTD, but also the iterative exchange of extrinsic state metrics. In this way, the proposed technique can accurately predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by the Monte Carlo simulation. The proposed technique offers new insights into the operation of FPTDs, which will facilitate improved designs in the future, in the same way as the conventional EXIT charts have enhanced the design and understanding of the conventional Log-BCJR turbo decoder

Implementation of a fully-parallel turbo decoder on a general-purpose graphics processing unit

Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In stateof- the-art turbo code implementations, the processing throughput is typically limited by the data dependencies that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly-serial Log-BCJR turbo decoder, we have recently proposed a novel Fully Parallel Turbo Decoder (FPTD) algorithm, which can eliminate the data dependencies and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support Single Instruction Multiple Data (SIMD) operation. This allows us to develop a novel General Purpose Graphics Processing Unit (GPGPU) implementation of the FPTD, which has application in Software-Defined Radios (SDRs) and virtualized Cloud- Radio Access Networks (C-RANs). As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times