Infrared testing of electronic components

Infrared testing of electronic component

Infrared testing of electronic components Final report, 5 Apr. 1965 - 5 Jun. 1966

Infrared radiation nondestructive test technique for electrical/electronic equipmen

Spring contact probes: wear characteristics testing for electrical and mechanical parameters

The study considers the development and evaluation of spring contact probes used for automated testing of printed circuit boards (PCBs) and assemblies. It considers the evolution of circuit technology which originated from the introduction of the thermionic valve at the beginning of the century. Since the introduction of the integrated circuit in the 1960's, the industry has seen considerable advances in integrated and printed circuit miniaturisation with its associated effect on the testability of the completed assembly. The close spacing between the tracks and pads within the printed circuit board, which is possibly loaded on both sides with integrated circuits and other components with fine pitch termination spacings, has initiated the rapid development of a specialised electronic test industry to ensure product quality. [Continues.

Ultra high speed image processing techniques

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels

EMI failure analysis techniques and noise prediction for trace crossing split planes

A variety of methods exist that help locate the source, coupling path, and antenna in an electromagnetic interference (EMI) problem. No single method is the best option in all cases. A good electromagnetic compatibility (EMC) engineer should understand and have experience with a wide range of failure analysis methods and thus, be able to select the most appropriate ones for a given problem. The first three papers are from a series of articles, which explains a set of methods for the analysis of EMI failures. Each method is categorized based on two criteria: 1) the elements in an EMI problem each method tries to determine: the source, coupling path or the antenna; 2) the complexity of each method. The methods are explained to guide EMC engineers in selecting the right one by evaluating the advantages and limitations of each method. Printed circuit boards (PCBs) often have high speed data traces crossing splits in the adjacent reference planes due to space limitations and cost constraints. These split planes usually result from different power islands on nearby layers. The fourth paper quantifies the effects of the split planes and the associated stitching capacitors for various stack-up configurations --Abstract, page iv

Index to NASA tech briefs, 1971

The entries are listed by category, subject, author, originating source, source number/Tech Brief number, and Tech Brief number/source number. There are 528 entries

Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Novel MCM Interconnection Analysis Using Capacitive Charge Generation (CCG)

A new SEM technique, Capacitive Charge Generation (CCG), has been developed to rapidly image MCM interconnection continuity. The new technique uses low primary electron beam energies (< 2.0 keV), very high beam currents (>100 nA), and fast electron beam scan rates (>5 frames/second) to probe buried conductors in MCMS. For these conditions, new surface charging effects have been observed that enable examination of conductors under thick insulating layers. CCG has been applied to conductors covered by over 90 {mu}m of polymer dielectric. The physics of CCG signal generation and applications for MCM failure analysis are described

Mitigation of glass weave skew using a combination of low DK spread glass, multi-ply dielectric and routing direction

As the data rates increase into the multi-gigabit range, the bit periods fall in the range of few tens of picoseconds. At above few Gbps, it becomes very important to reduce skew between differential pairs as it can adversely impact the signal eye and thereby increase bit error rate. The goal of this study is to mitigate the skew contributed by woven glass fabric of PCB dielectrics. The glass weave skew between differential pairs in a PCB occurs due to the difference in dielectric constants (DK) of glass and resin. This thesis aims to mitigate the skew by reducing the effective DK difference experienced by the traces of a differential pair. Several strategies like using low DK glass, spread glass styles with less gaps in the glass fabric, 1-ply and 2-ply dielectrics, routing the traces in warp and fill directions are studied through measurements taken on several test vehicles. Since the relative location of traces with respect to glass bundles cannot be controlled, it is highly unlikely to capture the worst case skew from measurements on few test vehicles. Full wave simulation model of laminate with fiber weave is employed. A systematic approach using measurements and simulations to mitigate the differential pair skew is presented --Abstract, page iii