6,287 research outputs found
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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
The first version Buffered Large Analog Bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors
Future detectors for high luminosity particle identification and ultra high
energy neutrino observation would benefit from a digitizer capable of recording
sensor elements with high analog bandwidth and large record depth, in a
cost-effective, compact and low-power way. A first version of the Buffered
Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons
learned from the development of the Large Analog Bandwidth Recorder and
Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has
been very successful and forms the basis of a generation of new, large-scale
radio neutrino detectors, its limited sampling depth is a major drawback. A
prototype has been designed and fabricated with 65k deep sampling at
multi-GSa/s operation. We present test results and directions for future
evolution of this sampling technique.Comment: 15 pages, 26 figures; revised, accepted for publication in NIM
Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel
Utilizing the hyperspace of noise-based logic, we show two string
verification methods with low communication complexity. One of them is based on
continuum noise-based logic. The other one utilizes noise-based logic with
random telegraph signals where a mathematical analysis of the error probability
is also given. The last operation can also be interpreted as computing
universal hash functions with noise-based logic and using them for string
comparison. To find out with 10^-25 error probability that two strings with
arbitrary length are different (this value is similar to the error probability
of an idealistic gate in today's computer) Alice and Bob need to compare only
83 bits of the noise-based hyperspace.Comment: Accepted for publication in European Journal of Physics B (November
10, 2010
A solid-state digital temperature recorder for space use
A solid-state, digital, temperature recorder has been developed for use in space experiments. The recorder is completely self-contained and includes a temperature sensor; all necessary electronics for signal conditioning, processing, storing, control and timing; and a battery power supply. No electrical interfacing with the particular spacecraft on which the unit is used is required. The recorder is small, light, and sturdy, and has no moving parts. It uses only biocompatible materials and has passed vibration and shock spaceflight qualification tests. The unit is capable of storing 2048, -10 to +45 C, 8-bit temperature measurements taken at intervals selectable by factors of 2 from 1.875 to 240 min; data can be retained for at least 6 months. The basic recorder can be simplified to accommodate a variety of applications by adding memory to allow more data to be recorded, by changing the front end to permit measurements other than temperature to be made, and by using different batteries to realize various operating periods. Stored flight data are read out from the recorder by means of a ground read-out unit
16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies
High speed, low power, and area efficient adders and comparators continue to play a key role in hardware implementation of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This thesis demonstrates a unique custom designed 16-bit adder in 250-nm CMOS technology to obtain fast and power/area efficient features by combining CPL and CS logic. Comparing the results obtained for proposed 16-bit Linear CPL/CS adder with the BEC (Binary Excess-1 Code) based low power SQRT-CS adder, the delay is reduced by approximately one thirds, power is reduced by 19.2%, and the number of transistors is reduced by 23.4%. Also, new tree-based 64-bit static and dynamic digital comparators are presented in this thesis to perform high speed and low power operations. This tree-based architecture combines a new approach of designing dynamic comparator using a low duty cycle clock to reduce the short circuit power consumption in pre-charge (or pre-discharge) mode. This work also introduces a new sizing strategy and load balancing techniques to improve self-pipelining tendency of a tree based design. A resource sharing technique is also integrated in both static and dynamic comparator designs. At 1.2V power supply in CMOS 90nm technology, worst path delay and worst power are 374ps and 822µW, respectively for low cost static design with 1244 (768+476) transistors in total. 768 transistors are used for resource sharing. The proposed full and partially dynamic designs show superior power efficiency compared to recent state of art designs. The worst power consumptions at 5GHz and 25% (50ps) duty cycle clock for the 64-bit full and partially dynamic comparator designs are 5.00mW and 2.78mW, respectively. 769 (320+449) transistors includes 320 transistors for resource sharing, and 1217 (768+449) includes 768 transistors for resource sharing for full and partial dynamic comparators, respectively
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Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies
This thesis focuses on low power and high speed design techniques for successive
approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale
CMOS technologies. SAR ADCs’ speed is limited by the number of bits of
resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed
up the conversion process, we introduce a radix-3 SAR ADC which can compute
1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently
hardware controlled radix-3 SAR ADC. We had to use two comparators per
cycle due to ADC architecture and we proposed a simple calibration scheme for
the comparators. Also, as the architecture of the DAC array is completely different
from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up
with an algorithm for calibration of capacitors of the DAC.
Low power SAR ADCs face two major challenges especially at high resolutions:
(1) increased comparator power to suppress the noise, and (2) increased
DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs.
To improve the comparator’s power efficiency, an efficient and low cost calibration
technique has been introduced. It allows a low power and noisy comparator to
achieve high signal-to-noise ratio (SNR).
To improve the DAC switching energy, we introduced a radix-3/radix-2
based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR
ADC and these two single ended DACs can be used as one differential DAC for
radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix-
2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2
search to reduce the DAC capacitor size and hence, to reduce switching power. It
can reduce the total number of unit capacitors by four times. Our proposed hybrid
SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR
ADCs. Also, to utilize technology scaling, we used the minimum capacitor size
allowed by thermal noise limitations. To achieve high resolution, we introduced
calibration algorithm for the DAC array.
As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional
radix-2 SAR ADC because of simultaneous use of two comparators. In
the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB
bits. So, the resolution required for radix-3 comparators are much larger than the
LSB value of 10-bit ADC. By implementing calibration of comparators, we can
use low power, high input referred offset and high speed comparators for radix-3
search. Radix-2 search will be used for rest of the bits and the resolution of the
radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search.
Also, we introduced clock gating for comparators. So, radix-3 comparators will not
toggle during radix-2 search and the radix-2 comparators will be inactive during
radix-3 search. By using the aforementioned techniques, the overall comparator
power is definitely less than a radix-3 SAR ADC and comparable to a conventional
radix-2 SAR ADC.
A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed
technique is designed and fabricated in 40nm CMOS technology. It achieves an
SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a
Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin
Synchronization trigger control system for flow visualization
The use of cinematography or holographic interferometry for dynamic flow visualization in an internal combustion engine requires a control device that globally synchronizes camera and light source timing at a predefined shaft encoder angle. The device is capable of 0.35 deg resolution for rotational speeds of up to 73 240 rpm. This was achieved by implementing the shaft encoder signal addressed look-up table (LUT) and appropriate latches. The developed digital signal processing technique achieves 25 nsec of high speed triggering angle detection by using direct parallel bit comparison of the shaft encoder digital code with a simulated angle reference code, instead of using angle value comparison which involves more complicated computation steps. In order to establish synchronization to an AC reference signal whose magnitude is variant with the rotating speed, a dynamic peak followup synchronization technique has been devised. This method scrutinizes the reference signal and provides the right timing within 40 nsec. Two application examples are described
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