Analysis of DVFS Techniques for Improving the GPU Energy Effi-ciency

Abstract Dynamic Voltage Frequency Scaling (DVFS) techniques are used to improve energy efficiency of GPUs. Literature survey and thorough analysis of various schemes on DVFS techniques during the last decade are presented in this paper. Detailed analysis of the schemes is included with respect to comparison of various DVFS techniques over the years. To endow with knowledge of various power management techniques that utilize DVFS during the last decade is the main objective of this paper. During the study, we find that DVFS not only work solely but also in coordination with other power optimization techniques like load balancing and task mapping where performance and energy efficiency are affected by varying the platform and benchmark. Thorough analysis of various schemes on DVFS techniques is presented in this paper such that further research in the field of DVFS can be enhanced

Voltage-Margin Advancements among Ultra-low Power Multicore CPU Generations

Ο κύριος σκοπός αυτής της μεταπτυχιακής εργασίας είναι ο πλήρης χαρακτηρισμός της συμπεριφοράς της 6ης γενιάς μικροεπεξεργαστή Skylake της Intel, με μια αξιολόγηση 10 δοκιμαστικών προγραμμάτων. Αυτή η αξιολόγηση τελείται μέσω μιας διαδικασίας σταδιακής μείωσης της τάσης του επεξεργαστή, πρώτα διατηρώντας τη μέγιστη συχνότητα στα 2.3 GHz και στη συνέχεια μειώνοντας την συχνότητα στο μισό (1.2 GHz). Η τελευταία περίπτωση μελετήθηκε με σκοπό την αποκάλυψη ακόμα χαμηλότερων ορίων τάσης, στα οποία το σύστημα λειτουργεί με κανονική συμπεριφορά με κόστος την χαμηλότερη απόδοση σε ταχύτητα. Ωστόσο, και στις δύο περιπτώσεις το ελάχιστο ασφαλές περιθώριο τάσης είναι 100 mV κάτω από την ονομαστική. Επιπλέον, αναλύουμε και αναφέρουμε εκτενώς κάθε περίπτωση οποιουδήποτε τύπου σφάλμα και κατάρρευση συστήματος. Στη συνέχεια, παρουσιάζουμε τα αποτελέσματα από τον χαρακτηρισμό της μηχανής Skylake, μαζί με αυτά που βρέθηκαν σε προηγούμενη μελέτη για τον 4ης γενιάς μικροεπεξεργαστή Haswell της Intel και παρουσιάζουμε την πρόοδο των περιθωρίων τάσης, ανάμεσα στις δύο γενιές επεξεργαστών εξαιρετικά χαμηλής ισχύος. Κατά την διαδικασία χαρακτηρισμού, συλλέξαμε επίσης μετρήσεις θερμοκρασίας και ισχύος. Τα αποτελέσματα παρουσιάζονται αναλυτικά μέσω μεταβολών από πυρήνα-σε-πυρήνα, κύκλωμα-σε-κύκλωμα και δοκιμασία-σε-δοκιμασία. Η μελέτη μας, δείχνει ότι κατά τη διάρκεια μείωσης της τάσης δεν σχηματίζονται περιοχές μη ασφαλούς λειτουργίας λόγω μη εμφάνισης διορθωμένων λαθών. Η μέγιστη μείωση τάσης που μπορεί να επιτευχθεί είναι 11.24% με εξαιρετικά κέρδη στην κατανάλωση ισχύος μέχρι και 41% για συγκεκριμένες παραμετροποιήσεις. Ωστόσο, σχετικά με την απόδοση της θερμοκρασίας παρατηρήθηκαν τόσο κέρδη όσο και απώλειες.The main goal of this master thesis is to fully characterize the behavior of Intel’s 6th generation Skylake microprocessor, during off-nominal voltage conditions. This characterization is conducted in stages through a CPU undervolting procedure, firstly by gradually reducing the voltage, while maintaining the maximum available frequency (2.3 GHz), and then by reducing the frequency at half (1.2 GHz). The latter, serves the purpose of exposing even lower voltage margins, in which the system operates in normal behavior while sacrificing speed performance. However, in both cases the minimum safe voltage margin is 100 mV below the nominal voltage. Furthermore, we extensively analyze and report any type of error and system crash occurrence. Afterwards, we present our Skylake characterization results along with those found in a previous study conducted for Intel’s 4th generation Haswell microprocessor and we present the voltage-margin advancements between the two ultra-low power CPU generations. During the characterization, we also collected temperature and power measurements. The results are demonstrated in detail through core-to-core, chip-to-chip and benchmark-to-benchmark variations. Our study shows that during the voltage reduction, unsafe operation regions are not formed due to lack of corrected errors occurrences. The maximum voltage reduction that can be achieved is 11.24% with exceptional power consuming gains of up to 41% for specific configurations. However, regarding temperature efficiency there were observed both gains and losses

Power Bounded Computing on Current & Emerging HPC Systems

Power has become a critical constraint for the evolution of large scale High Performance Computing (HPC) systems and commercial data centers. This constraint spans almost every level of computing technologies, from IC chips all the way up to data centers due to physical, technical, and economic reasons. To cope with this reality, it is necessary to understand how available or permissible power impacts the design and performance of emergent computer systems. For this reason, we propose power bounded computing and corresponding technologies to optimize performance on HPC systems with limited power budgets. We have multiple research objectives in this dissertation. They center on the understanding of the interaction between performance, power bounds, and a hierarchical power management strategy. First, we develop heuristics and application aware power allocation methods to improve application performance on a single node. Second, we develop algorithms to coordinate power across nodes and components based on application characteristic and power budget on a cluster. Third, we investigate performance interference induced by hardware and power contentions, and propose a contention aware job scheduling to maximize system throughput under given power budgets for node sharing system. Fourth, we extend to GPU-accelerated systems and workloads and develop an online dynamic performance & power approach to meet both performance requirement and power efficiency. Power bounded computing improves performance scalability and power efficiency and decreases operation costs of HPC systems and data centers. This dissertation opens up several new ways for research in power bounded computing to address the power challenges in HPC systems. The proposed power and resource management techniques provide new directions and guidelines to green exscale computing and other computing systems

Dynamic Hardware Resource Management for Efficient Throughput Processing.

High performance computing is evolving at a rapid pace, with throughput oriented processors such as graphics processing units (GPUs), substituting for traditional processors as the computational workhorse. Their adoption has seen a tremendous increase as they provide high peak performance and energy efficiency while maintaining a friendly programming interface. Furthermore, many existing desktop, laptop, tablet, and smartphone systems support accelerating non-graphics, data parallel workloads on their GPUs. However, the multitude of systems that use GPUs as an accelerator run different genres of data parallel applications, which have significantly contrasting runtime characteristics. GPUs use thousands of identical threads to efficiently exploit the on-chip hardware resources. Therefore, if one thread uses a resource (compute, bandwidth, data cache) more heavily, there will be significant contention for that resource. This contention will eventually saturate the performance of the GPU due to contention for the bottleneck resource,leaving other resources underutilized at the same time. Traditional policies of managing the massive hardware resources work adequately, on well designed traditional scientific style applications. However, these static policies, which are oblivious to the application’s resource requirement, are not efficient for the large spectrum of data parallel workloads with varying resource requirements. Therefore, several standard hardware policies such as using maximum concurrency, fixed operational frequency and round-robin style scheduling are not efficient for modern GPU applications. This thesis defines dynamic hardware resource management mechanisms which improve the efficiency of the GPU by regulating the hardware resources at runtime. The first step in successfully achieving this goal is to make the hardware aware of the application’s characteristics at runtime through novel counters and indicators. After this detection, dynamic hardware modulation provides opportunities for increased performance, improved energy consumption, or both, leading to efficient execution. The key mechanisms for modulating the hardware at runtime are dynamic frequency regulation, managing the amount of concurrency, managing the order of execution among different threads and increasing cache utilization. The resultant increased efficiency will lead to improved energy consumption of the systems that utilize GPUs while maintaining or improving their performance.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113356/1/asethia_1.pd