Design And Analysis Of Low Noise Amplifier Using Cadence

Low Noise Amplifier also known as LNA is one of the most significant component for application in wireless communication system. It is a very important part in RF receiver because it can reduce noise of gain by the amplifier when the noise of the amplifier is received directly. The low noise amplifier has been designed to get the better performance by follow the requirement in this new era consists of high gain, low noise figure, lower power consumption, small chip area, low cost and good input and output matching. In this research, a LNA schematic consists of three stages which are common gate amplifier, common drain amplifier and active inductor is designed to mitigate this constraint. Common gate and common drain are used for input and output stages in every LNA. Both are also used for excellent input and output matching and have a potential to get a lower noise whereas for active inductor, it is used to obtain the lower power consumption and to reduce the chip size in layout design. The results show that the proposed LNA is able to achieve the best performance with a simulated gain of 14.7dB, extremely lower power consumption of 0.8mW, noise figure of 7dB and small chip area 0.26mm². Consequently, this modified LNA is appropriate for low-voltage applications especially in wireless communication system

Low Power Operational Amplifier In 0.13um Technology

Low power is one of the most indispensable criteria in several of application. In this paper a low power operational amplifier consists of two stages and operates at 1.8V power. It is designed to meet a set of provided specification such as high gain and low power consumption. Designers are able to work at low input bias current and also at low voltage due to the unique behavior of the MOS transistors in sub-threshold region. This two-stage op-amp is designed using the Silterra 130nm technology library. The layout has been draw and its area had been calculated. The proposed two stage op-amp consists of NMOS current mirror as bias circuit, differential amplifier as the first stage and common source amplifier as the second stage. The first stage of an op-amp contributed high gain while the second stage contributes a moderate gain. The results show that the circuit is able to work at 1.8V power supply voltage (VDD) and provides gain of 69.73dB and 28.406MHz of gain bandwidth product for a load of 2pF capacitor. Therefore, the power dissipation and the consistency of this operational amplifier are better than previously reported operational amplifier

Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications

Reader Design for Chipless Millimeter-Wave Identification (MMID)TAG

RÉSUMÉ L’identification par radiofréquence (RFID) est une technologie d'identification qui a de nombreuses applications utiles telles que le suivi des marchandises et les contrôles d’accès. RFID est une technique de transmission et réception à courte distance « sans-contact » pour envoyer des données ID à un lecteur à partir d’un objet marqué. Un système RFID se compose d’une étiquette de support de données, un lecteur, un middleware et une application d'entreprise. Tout d'abord, le signal transmis est généré par le lecteur, après une certaine distance de transmission dans l'espace libre, l’étiquette reçoit le signal détecté et après le traitement de signal ou codage du signal sur l'étiquette, le signal codé est renvoyé au lecteur. La réception et le traitement du signal seront finalement faits au récepteur. Cependant, la technologie RFID est entravée en raison de son prix élevé. Les étiquettes RFID sans puce résolvent le problème de coût et ont le potentiel de pénétrer aux marchés en grand public pour l’étiquetage de l’article à faible coût. Pour les étiquettes sans puce il n'y a pas de traitement de signal. Le traitement du signal se fait uniquement au niveau du lecteur. Ainsi, un lecteur qui est utilisé pour communiquer avec l’étiquette est également important dans un système de communication. Le domaine de fréquence ou la signature spectrale en fonction des étiquettes sans puce est un type d’étiquette sans puce. D'autre part, l'émetteur et le récepteur se composent d'un lecteur. Basé sur le principe de fonctionnement des étiquettes sans puce dans le domaine de fréquence, un lecteur comprend un émetteur et un récepteur utilisés pour communiquer avec une étiquette de fréquence et est présenté dans cette thèse. Tout d'abord, le principe de fonctionnement détaillé du système MMID sans puce, dans le domaine fréquentiel est introduit. D'autre part, sur la base du principe de fonctionnement, les spécifications de la conception du lecteur sont proposées. Plusieurs topologies différentes de la conception du lecteur seront comparées et la meilleure topologie sera sélectionnée pour la conception du lecteur. En second lieu, sur la base des spécifications du système de lecture et de la topologie sélectionnée, les résultats de simulation de la structure sélectionnée de lecteur sont présentés. Après les simulations, la conception du chaque composant est montré. Dans cette conception de système des circuits, tous les circuits passifs sont conçus et simulés dans HFSS et mesurés sur VNA. Tous les circuits actifs sont des puces commerciale de différentes compagnies. Les résultats des simulations et mesures de chaque circuit passif sont affichés.----------ABSTRACT Radiofrequency identification (RFID) technology is an identification technology that has many useful applications such as tracking goods and access controls. RFID is a touchless, short distance transmission and reception technique for ID data that is sent from a labeled object to a reader. A data-carrying tag, a reader, middleware and an enterprise application would make up a RFID system. Firstly, the transmitted signal is generated by the reader, the tag receiver, after a certain distance of transmission in free space, a detected signal and after processing signal or encoding signal on the tag, the encoded signal is then sent back to the reader. Signal receiving and processing part will be finally processed in the receiver. However, the RFID technology is hindered because of its high price tag. Chipless RFID tags solve the cost issues and have the potential to penetrate into mass markets for low-cost item tagging. For chipless tags, there is no signal processing in tags, the signal processing is done only in the reader. So a reader, which is used to communicate with the tag, is also important in a communication system. Frequency domain or spectral signature-based chipless tags are some kinds of chipless tag. On the other hand, transmitter and receiver are the core parts of a reader, based on the working principle of frequency domain chipless tags, a reader that includes a transmitter and a receiver used to communicate with frequency tag is presented in this dissertation. First of all, the detailed working principle of a chipless MMID system in the frequency domain is introduced. Based on the working principle, the specifications of the reader design are proposed. Several different topologies of the reader design will be compared and the best topology will be selected for our reader design. Secondly, based on the specifications of the reader system and the selected topology, the simulation results of the selected structure of the reader are presented. After the simulations, the design of each component is shown. In this system design, all the passive circuits are designed and simulated in HFSS and tested on VNA. All the active circuits are commercial chips from different companies. Simulation and measurement results for each passive circuit are given. Finally, the whole circuits including designed passive circuits and active circuits are integrated into a system board to create a reader system. There are two system boards finally fabricated, one transmitter board and one completed reader board. The transmitter board is tested firstly. Upon achieving good results of the transmitter board, the whole transceiver board is tested finally

Analysis and Design of Silicon based Integrated Circuits for Radio Frequency Identification and Ranging Systems at 24GHz and 60GHz Frequency Bands

This scientific research work presents the analysis and design of radio frequency (RF) integrated circuits (ICs) designed for two cooperative RF identification (RFID) proof of concept systems. The first system concept is based on localizable and sensor-enabled superregenerative transponders (SRTs) interrogated using a 24GHz linear frequency modulated continuous wave (LFMCW) secondary radar. The second system concept focuses on low power components for a 60GHz continuous wave (CW) integrated single antenna frontend for interrogating close range passive backscatter transponders (PBTs). In the 24GHz localizable SRT based system, a LFMCW interrogating radar sends a RF chirp signal to interrogate SRTs based on custom superregenerative amplifier (SRA) ICs. The SRTs receive the chirp and transmit it back with phase coherent amplification. The distance to the SRTs are then estimated using the round trip time of flight method. Joint data transfer from the SRT to the interrogator is enabled by a novel SRA quench frequency shift keying (SQ-FSK) based low data rate simplex communication. The SRTs are also designed to be roll invariant using bandwidth enhanced microstrip patch antennas. Theoretical analysis is done to derive expressions as a function of system parameters including the minimum SRA gain required for attaining a defined range and equations for the maximum number of symbols that can be transmitted in data transfer mode. Analysis of the dependency of quench pulse characteristics during data transfer shows that the duty cycle has to be varied while keeping the on-time constant to reduce ranging errors. Also the worsening of ranging precision at longer distances is predicted based on the non-idealities resulting from LFMCWchirp quantization due to SRT characteristics and is corroborated by system level measurements. In order to prove the system concept and study the semiconductor technology dependent factors, variants of 24GHz SRA ICs are designed in a 130nm silicon germanium (SiGe) bipolar complementary metal oxide technology (BiCMOS) and a partially depleted silicon on insulator (SOI) technology. Among the SRA ICs designed, the SiGe-BiCMOS ICs feature a novel quench pulse shaping concept to simultaneously improve the output power and minimum detectable input power. A direct antenna drive SRA IC based on a novel stacked transistor cross-coupled oscillator topology employing this concept exhibit one of the best reported combinations of minimum detected input power level of −100 dBm and output power level of 5.6 dBm, post wirebonding. The SiGe stacked transistor with base feedback capacitance topology employed in this design is analyzed to derive parameters including the SRA loop gain for design optimization. Other theoretical contributions include the analysis of the novel integrated quench pulse shaping circuit and formulas derived for output voltage swing taking bondwire losses into account. Another SiGe design variant is the buffered antenna drive SRA IC having a measured minimum detected input power level better than −80 dBm, and an output power level greater than 3.2 dBm after wirebonding. The two inputs and outputs of this IC also enables the design of roll invariant SRTs. Laboratory based ranging experiments done to test the concepts and theoretical considerations show a maximum measured distance of 77m while transferring data at the rate of 0.5 symbols per second using SQ-FSK. For distances less than 10m, the characterized accuracy is better than 11 cm and the precision is better than 2.4 cm. The combination of the maximum range, precision and accuracy are one of the best reported among similar works in literature to the author’s knowledge. In the 60GHz close range CW interrogator based system, the RF frontend transmits a continuous wave signal through the transmit path of a quasi circulator (QC) interfaced to an antenna to interrogate a PBT. The backscatter is received using the same antenna interfaced to the QC. The received signal is then amplified and downconverted for further processing. To prove this concept, two optimized QC ICs and a downconversion mixer IC are designed in a 22nm fully depleted SOI technology. The first QC is the transmission lines based QC which consumes a power of 5.4mW, operates at a frequency range from 56GHz to 64GHz and occupies an area of 0.49mm2. The transmit path loss is 5.7 dB, receive path gain is 2 dB and the tunable transmit path to receive path isolation is between 20 dB and 32 dB. The second QC is based on lumped elements, and operates in a relatively narrow bandwidth from 59.6GHz to 61.5GHz, has a gain of 8.5 dB and provides a tunable isolation better than 20 dB between the transmit and receive paths. This QC design also occupies a small area of 0.34mm² while consuming 13.2mW power. The downconversion is realized using a novel folded switching stage down conversion mixer (FSSDM) topology optimized to achieve one of the best reported combination of maximum voltage conversion gain of 21.5 dB, a factor of 2.5 higher than reported state-of-the-art results, and low power consumption of 5.25mW. The design also employs a unique back-gate tunable intermediate frequency output stage using which a gain tuning range of 5.5 dB is attained. Theoretical analysis of the FSSDM topology is performed and equations for the RF input stage transconductance, bandwidth, voltage conversion gain and gain tuning are derived. A feasibility study for the components of the 60GHz integrated single antenna interrogator frontend is also performed using PBTs to prove the system design concept.:1 Introduction 1 1.1 Motivation and Related Work . . . . . . . . . . . . . . . . . . . . . 1 1.2 Scope and Functional Specifications . . . . . . . . . . . . . . . . . 4 1.3 Objectives and Structure . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Features and Fundamentals of RFIDs and Superregenerative Amplifiers 9 2.1 RFID Transponder Technology . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Chipless RFID Transponders . . . . . . . . . . . . . . . . . 10 2.1.2 Semiconductor based RFID Transponders . . . . . . . . . . 11 2.1.2.1 Passive Transponders . . . . . . . . . . . . . . . . 11 2.1.2.2 Active Transponders . . . . . . . . . . . . . . . . . 13 2.2 RFID Interrogator Architectures . . . . . . . . . . . . . . . . . . . 18 2.2.1 Interferometer based Interrogator . . . . . . . . . . . . . . . 19 2.2.2 Ultra-wideband Interrogator . . . . . . . . . . . . . . . . . . 20 2.2.3 Continuous Wave Interrogators . . . . . . . . . . . . . . . . 21 2.3 Coupling Dependent Range and Operating Frequencies . . . . . . . 25 2.4 RFID Ranging Techniques . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.0.1 Received Signal Strength based Ranging . . . . . 28 2.4.0.2 Phase based Ranging . . . . . . . . . . . . . . . . 30 2.4.0.3 Time based Ranging . . . . . . . . . . . . . . . . . 30 2.5 Architecture Selection for Proof of Concept Systems . . . . . . . . 32 2.6 Superregenerative Amplifier (SRA) . . . . . . . . . . . . . . . . . . 35 2.6.1 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 42 2.6.3 Frequency Domain Characteristics . . . . . . . . . . . . . . 45 2.7 Semiconductor Technologies for RFIC Design . . . . . . . . . . . . 48 2.7.1 Silicon Germanium BiCMOS . . . . . . . . . . . . . . . . . 48 2.7.2 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . 48 3 24GHz Superregenerative Transponder based Identification and Rang- ing System 51 3.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 SRT Identification and Ranging . . . . . . . . . . . . . . . . 51 3.1.2 Power Link Analysis . . . . . . . . . . . . . . . . . . . . . . 55 3.1.3 Non-idealities . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.4 SRA Quench Frequency Shift Keying for data transfer . . . 61 3.1.5 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 Low Power Direct Antenna Drive CMOS SRA IC . . . . . . 66 3.2.1.1 Circuit analysis and design . . . . . . . . . . . . . 66 3.2.1.2 Characterization . . . . . . . . . . . . . . . . . . . 69 3.2.2 Direct Antenna Drive SiGe SRA ICs . . . . . . . . . . . . . 71 3.2.2.1 Stacked Transistor Cross-coupled Quenchable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.2.1.1 Resonator . . . . . . . . . . . . . . . . . . 72 3.2.2.1.2 Output Network . . . . . . . . . . . . . . 75 3.2.2.1.3 Stacked Transistor Cross-coupled Pair and Loop Gain . . . . . . . . . . . . . . . . . 77 3.2.2.2 Quench Waveform Design . . . . . . . . . . . . . . 85 3.2.2.3 Characterization . . . . . . . . . . . . . . . . . . . 89 3.2.3 Antenna Diversity SiGe SRA IC with Integrated Quench Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2.3.1 Circuit Analysis and Design . . . . . . . . . . . . 91 3.2.3.1.1 Crosscoupled Pair and Sampling Current 94 3.2.3.1.2 Common Base Input Stage . . . . . . . . 95 3.2.3.1.3 Cascode Output Stage . . . . . . . . . . . 96 3.2.3.1.4 Quench Pulse Shaping Circuit . . . . . . 96 3.2.3.1.5 Power Gain . . . . . . . . . . . . . . . . . 99 3.2.3.2 Characterization . . . . . . . . . . . . . . . . . . . 102 3.2.4 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 103 3.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 106 3.3.1 Superregenerative Transponders . . . . . . . . . . . . . . . 106 3.3.1.1 Bandwidth Enhanced Microstrip Patch Antennas 108 3.3.2 FMCW Radar Interrogator . . . . . . . . . . . . . . . . . . 114 3.3.3 Chirp Z-transform Based Data Analysis . . . . . . . . . . . 116 4 60GHz Single Antenna RFID Interrogator based Identification System 121 4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1 Quasi-circulator ICs . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1.1 Transmission Lines based Quasi-Circulator IC . . 126 4.2.1.2 Lumped Elements WPD based Quasi-Circulator . 130 4.2.1.3 Characterization . . . . . . . . . . . . . . . . . . . 134 4.2.1.4 Knowledge Gained . . . . . . . . . . . . . . . . . . 135 4.2.2 Folded Switching Stage Downconversion Mixer IC . . . . . 138 4.2.2.1 FSSDM Circuit Design . . . . . . . . . . . . . . . 138 4.2.2.2 Cascode Transconductance Stage . . . . . . . . . . 138 4.2.2.3 Folded Switching Stage with LC DC Feed . . . . . 142 4.2.2.4 LO Balun . . . . . . . . . . . . . . . . . . . . . . . 145 4.2.2.5 Backgate Tunable IF Stage and Offset Correction 146 4.2.2.6 Voltage Conversion Gain . . . . . . . . . . . . . . 147 4.2.2.7 Characterization . . . . . . . . . . . . . . . . . . . 150 4.2.2.8 Knowledge Gained . . . . . . . . . . . . . . . . . . 151 4.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 154 5 Experimental Tests 157 5.1 24GHz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Ranging Experiments . . . . . . . . . . . . . . . . . . . . . 157 5.1.2 Roll Invariance Experiments . . . . . . . . . . . . . . . . . . 158 5.1.3 Joint Ranging and Data Transfer Experiments . . . . . . . 158 5.2 60GHz System Detection Experiments . . . . . . . . . . . . . . . . 165 6 Summary and Future Work 167 Appendices 171 A Derivation of Parameters for CB Amplifier with Base Feedback Capac- itance 173 B Definitions 177 C 24GHz Experiment Setups 179 D 60 GHz Experiment Setups 183 References 185 List of Original Publications 203 List of Abbreviations 207 List of Symbols 213 List of Figures 215 List of Tables 223 Curriculum Vitae 22

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies

Optical wireless data transfer for rotor detection and diagnostics

A special application of optical wireless data transfer, namely on-line monitoring and diagnostic of rotors in turbines and engines, has been considered in this thesis. In this application, to maintain line of sight, i.e. data transfer, between a sensor placed on a rotating component inside the turbine and a monitoring point placed in a fixed position outside the turbine, a periodic fast fading channel is generated, which gives the transceivers more flexibility regarding their mounting location. The communication in such a channel is affected by the intermittency and variation of the signal power, which produces a unique channel condition that influences the performance of the optical transceiver. To investigate the channel condition and the error rate of the periodic fast fading channel with signal fluctuation, a model is developed to simulate the optical channel by considering the variation of signal power as a result of the change in the relative position of the photodiode with respect to the Lambertian radiation pattern of the LED, in a simplified linear geometry. The error rate is estimated using the Saddlepoint approximation on a specific threshold strategy. The results show that the channel can afford the sensor data transmission and the performance can be improved by modifying several parameters, such as geometrical distance, transmitter power and load resistor. Compared to a normal channel, a higher load resistor on the photodiode front end has the advantage of decreasing the noise level and increasing the data capacity in the fast fading channel. The analysis of the automatic gain control amplifier indicates that a higher load resistor needs a lower loop gain and from the model of the Transimpedance amplifier (TIA), the bandwidth extension from the amplifier is more significant for a higher resistor. In addition to the theoretical model, an experimental setup is built to emulate the channel in practice. The degree of similarity between the experimental setup and the theoretical model of the channel is estimated from the comparison of the generated communication windows. Since it has been found that differences exist in the duration of the communication window and the variation of the signal power, scaling factors to ensure their compatibility have been derived. Transceiver hardware which implemented the modelled functionality has been developed and a protocol to establish the communication with the required error rate has been proposed. Using the hardware implementation, a detection method for both rising and falling edges of the signal pulses and a threshold strategy have been demonstrated. The device power consumption is also estimated. What is more, the electromagnetic environment of a squirrel cage motor is simulated using the finite element method to investigate the interference and the possibility of providing power to the IR communication devices using power scavenging. In the conclusion, the key findings of the thesis are summarised. A solution is proposed for sensor data transfer using an optical channel for rotor monitoring applications, which involves the design of the IR transceiver, the implementation of the developed protocol and the power consumption estimation

Design of Beam Steering Electronic Circuits for Medical Applications

This thesis deals with the theory and design of a hemispherical antenna array circuit that is capable to operate in the intermediate zones. By doing that, this array can be used in Hyperthermia Treatment for Brain Cancer in which the aim is to noninvasively focus the fields at microwave frequencies to the location of the tumor cells in the brain. Another possible application of the array is to offer an alternative means of sustaining Deep Brain Stimulation other than using the traditional (surgical) approach. The new noninvasive technique is accomplished by the use of a hemispherical antenna array placed on the human's head. The array uses a new beamforming technique that achieves 3 dimensional beamforming or focusing of the magnetic field of antennas to desired points in the brain to achieve either cell death by temperature rise (Hyperthermia Application) or to cause brain stimulation and hopefully alleviate the affects of Parkinson's Disease (Deep Brain Stimulation). The main obstacle in this design was that the far field approximation that is usually used when designing antenna arrays does not apply in this case since the hemispherical array is in close proximity to where the magnetic field is desired to be focused. The antenna array problem is approached as a boundary-valued problem with the human head being modeled as a three layered hemisphere. The exact expressions for electromagnetic fields are derived. Health issues such as electric field exposure and specific absorption rate (SAR) are considered. After developing the main antenna and beamforming theory, a neural network is designed to accomplish the beamforming technique used. The radio-frequency (RF) transmitter was designed to transmit the fields at a frequency of 1.8 GHz. The antenna array can also be used as a receiver. The antenna and beamforming theory is presented. A new reception technique is shown which enables the array to receive multiple magnetic field sources from within the hemispherical surface. The receiver is designed to operate at 500 kHz with the RF receiver circuit designed to receive any signal from within the hemispherical surface at a frequency of 500 kHz

A 3.1-4.8GHz IR-UWB All-Digital Pulse Generator in 0.13-um CMOS Technology for WBAN Systems

Analog, Digital & RF Circuit DesignImpulse Radio Ultra-WideBand (IR-UWB) systems have drawn growing attention for wireless sensor networks such as Wireless Personal Area Network (WPAN) and Wireless Body Area Network (WBAN) systems ever since the Federal Communications Commission (FCC) released the spectrum between 3.1 and 10.6GHz for unlicensed use in 2002. The restriction on transmitted power spectral density in this band is equal to the noise emission limit of household digital electronics. This band is also shared with several existing service, therefore in-band interference is expected and presents a challenge to UWB system design. UWB devices as secondary spectrum users must also detect and avoid (DAA) other licensed users from the cognitive radio???s point of view. For the DAA requirement, it is more effective to deploy signal with variable center frequency and a minimum 10dB bandwidth of 500MHz than a signal covering the entire UWB spectrum range with fixed center frequency. A key requirement of the applications using IR-UWB signal is ultra-low power consumption for longer battery life. Also, cost reduction is highly desirable. Recently, digital IR-UWB pulse generation is studied more than analog approach due to its lower power consumption. An all-digital pulse generator in a standard 0.13-um CMOS technology for communication systems using Impulse Radio Ultra-WideBand (IR-UWB) signal is presented. A delay line-based architecture utilizing only static logic gates and leading lower power consumption for pulse generation is proposed in this thesis. By using of all-digital architecture, energy is consumed by CV2 switching losses and sub-threshold leakage currents, without RF oscillator or analog bias currents. The center frequency and the fixed bandwidth of 500MHz of the output signal can be digitally controlled to cover three channels in low band of UWB spectrum. Delay based Binary Shift Keying (DB-BPSK) and Pulse Position Modulation (PPM) schemes are exploited at the same time to modulate the transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48pJ/pulse at 1.2V supply voltage, which is well suitable for WBAN systems.ope