250 MHz Multiphase Delay Locked Loop for Low Power Applications

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz

A high level synthesis of a fibre channel core for a system-on-chip implementation.

A high performance standardized System-on-Chip (SoC ) communication system has been developed as an embedded core. A high level synthesis of a Fibre Channel core has been realized that takes advantage of the performance advantages and specifications associated with the Fibre Channel protocol. A soft IP core of a Fibre Channel port is presented in the form of a register transfer level (RTL) descriptor language which can be implemented in arbitrary target technologies. A full-speed (1.0625 GHz link clock) sign-off quality tape-out of the design in TSMC\u27s 0.18 mum technology has been carried out using a design flow centered on the Cadence SoC Encounter platform. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .K84. Source: Masters Abstracts International, Volume: 44-03, page: 1456. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005