Design of two-stage class AB CMOS buffers: a systematic approach

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW)

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

A Piecewise Linear Approximation D/A Converter for Small Format LCD Applications

Low power operation is a driving requirement for the advancement of portable consumer electronics. As products get smaller and have more functionality the device integration requirements get tighter. This is certainly true of small format LCD applications like PDAs and cell phones. Recent advances in LCD technology have allowed for advanced circuitry to be built on the glass. This allows for the unique opportunity to integrate the LCD column driver with other circuitry rather than the traditional flip chip mounting on the glass. The integration of these D/A converters with digital circuitry presents a new set of design considerations. These considerations allow for the exploration of non-traditional architectures and algorithms. This work will explore these design considerations in detail and present a novel algorithm for conversion as well as a system implementation of this algorithm. The system implementation is compared to a standard linear converter to weigh the relative advantages of each. A high performance dynamically biased amplifier is developed for use in the D/A converter. This amplifier has a high slew rate while consuming a small amount of quiescent power

Design of High-Bandwidth and High-Linearity Input Buffers for ADCs

Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized with a higher voltage supply than that of the core voltage of the technology, mainly for linearity purposes. This, in turn, makes it mandatory to have more than one voltage source to supply a single chip in addition to having devices capable of handling higher voltages. This work explores the possibility of having IBs supplied with the technology’s core voltage to standardize all of the devices and reducing the different voltage supply sources and/or voltage regulators needed for operating the front-end drivers of the Analog to Digital Converters (ADCs). A new input buffer architecture will be presented and compared to some prior input buffer implementations in the same conditions. This new architecture presents good linearity and bandwidth results and can be used for input buffers with the added benefit of not needing higher voltages nor special devices. This new architecture is based off an existing one with another feedback loop to improved high-frequency peaking and linearity issues. This architecture achieves better results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak differential. Furthermore, this buffer achieves a better efficiency linearity-wise when comparing to other buffers in the same conditions

Class-G Headphone Amplifier Architectures

To maximize the battery life of portable audio devices like iPods, MP3 players and mobile phones, there is a need for audio power amplifiers with low quiescent power, high efficiency along with uncompromising quality (Distortion performance/ THD) and low cost. Despite their high efficiency, Class-D amplifiers are undesirable as headphone drivers in mobile devices, owing to their high EMI radiation, additional costs due to filtering required at the output and also their poor linearity at small signal levels. Almost all of todays headphone drivers are Class-AB linear amplifiers, with poor efficiencies. Here we propose a Class-G linear amplifier, which uses rail switching to improve efficiency. It can be viewed as a Class-AB amplifier operating from the lower supply and a Class-C amplifier from the higher supply. Though the classical definition of efficiency using full-scale sine wave does not show much improvement for Class-G (85.9 percent) over Class-AB (78 percent), we demonstrate that the Class-G audio amplifiers can have significant improvement of efficiencies (battery life) in the practical sense. By considering the amplitude distribution of audio signals a new realistic definition of efficiency has been proposed. This definition helps in demonstrating the advantage of using Class-G over Class-AB and also helps in optimizing the choice of supply voltages which is critical to maximizing the efficiency of Class-G amplifiers. Two new circuit topologies have been proposed and thoroughly investigated. The first circuit is more like a developmental stage and is designed/fabricated in AMI 0.5um. The second proposed Class-G amplifier with modified Class-AB bias, implemented in IBM 90nm, achieves -82.5dB THD N by seamless supply switching and uses the least reported quiescent power (350 mu W) and area (0.08mm^2)