Порівняльний аналіз baseband-процесорів для реалізації SDR-трансиверів

Проведено порівняльний аналіз обчислювальних засобів для їх подальшого використання у ролі baseband-процесору для трансивера типу Software Defined Radio. Встановлено, що для цієї ролі можна використати процесори загального користування у парі з графічними процесорами, що мають високу гнучкість у проектуванні, але низьку швидкодію та високе енергоспоживання. Використання спеціальних процесорів обробки сигналів надає перевагу у кращому енергоспоживанні, що надає можливість використовувати їх для швидкої розробки портативних трансиверів з достатньо низкою ціною. Для високопродуктивних трансиверів краще за все використовувати програмовані логічні інтегральні схеми, що за рахунок високого паралелізму надують суттєвий виграш у швидкодії. Запропонована власна архітектура трансивера з використанням системи-на-кристалі та радіочастотного трансивера для побудови гнучкої системи передачі інформації по безпровідному каналу зв’язку.Software-defined Radio is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Consequently, Software-defined Radio has earned a lot of attention and is of great significance to both academia, military and aerospace industry. Components of Softwaredefined Radio (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) implemented by means of software on a personal computer or embedded system. Operation of signal processing are handed over to the baseband processor, rather than being done in special electronic circuits. Baseband processors are implemented through employing various types of hardware platforms, such as General Purpose Processors, Graphics Processing Units, Digital Signal Processors, and Field Programmable Gate Arrays. Each of these platforms is associated with their own set of advantages and disadvantages. In this paper was proposed a comparison of the state-of-the-art hardware platforms in the context of implementation Softwaredefined Radio transceivers. For comparison was determined as follow criteria: computational power of hardware platform, power consumption, complexity of developing, and cost of tools and equipment. First approaches to realizing baseband processors is using a General Purpose Processor and accelerating by Graphics Processing Units. But General Purpose Processor and Graphics Processing Units execute software instructions in the sequential order. For this reason, General Purpose Processors are not convenient for high-throughput computing with real-time requirements. Also this hardware platforms have increased power consumption. This aspect does not allow use General Purpose Processor and Graphics Processing Units in small and portable Software-defined Radio transceivers. In other hand, General Purpose Processors are preferable hardware platform by researchers and beginners due to their flexibility and programmability. Therefore, General Purpose Processors and Graphics Processing Units is highly recommended for prototyping Software-defined Radio platforms. Digital Signal Processor was reviewed as alternative approach for implementing baseband processors. Digital Signal Processors is a particular type of General Purpose Processors that is optimized to process digital signals. Digital Signal Processors have similar disadvantage with insufficient computational power, but some manufacturer sell energy optimized Digital Signal Processors. Consequently, Digital Signal Processor is commonly used in small and portable Software-defined Radio transceivers. Field Programmable Gate Arrays and System-on-Chips with Field Programmable Gate Array are strongly recommended for high-performance Software-defined Radio platforms. This hardware platforms combine the flexibility of processors and efficiency of small Digital Signal Processor. Field Programmable Gate Arrays can achieve a high level of parallelism in executing digital signal processing. However, the designers must have a high degree in digital electronics and good acknowledgement of hardware description languages. After the research, was proposed own flexible architecture Softwaredefined Radio transceiver and methods for development

Techniques for Low-latency in Software-defined Radio-based Networks

Decreased budgets have pushed the United States Air Force towards using existing systems in new ways. The use of unmanned aerial vehicle swarms is one example of reuse of existing systems. One problem with the increased utilization of these swarms is the congestion of the electromagnetic spectrum. Software-defined or cognitive radios have been proposed as a basis for a potential robust communications solution. The present research aims to develop and test a genetic algorithm-based cognitive engine to begin looking at real-time engines that could be used in future swarms. Here, latency is the optimization objective of primary importance. In testing the engine, particular items of interest include the number of solutions evaluated in a given bound and the engine\u27s reliability in yielding acceptable network performance. Initial experiments indicate the engine can consider significant portions of the search space within a relatively small bound and that the engine is efficient at finding highly fit solutions. Future work for this research includes evaluating how well high fitness correlates to acceptable performance and testing the engine with additional noise floors

Comparative study of tool-flows for rapid prototyping of software-defined radio digital signal processing

This dissertation is a comparative study of tool-flows for rapid prototyping of SDR DSP operations on programmable hardware platforms. The study is divided into two parts, focusing on high-level tool-flows for implementing SDR DSP operations on FPGA and GPU platforms respectively. In this dissertation, the term ‘tool-flow’ refers to a tool or a chain of tools that facilitate the mapping of an application description specified in a programming language into one or more programmable hardware platforms. High-level tool-flows use different techniques, such as high-level synthesis to allow the designer to specify the application from a high level of abstraction and achieve improved productivity without significant degradation in the design’s performance. SDR is an emerging communications technology that is driven by - among other factors – increasing demands for high-speed, interoperable and versatile communications systems. The key idea in SDR is the need to implement as many as possible of the radio functions that were traditionally defined in fixed hardware, in software on programmable hardware processors instead. The most commonly used processors are based on complex parallel computing architectures in order to support the high-speed processing demands of SDR applications, and they include FPGAs, GPUs and multicore general-purpose processors (GPPs) and DSPs. The architectural complexity of these processors results in a corresponding increase in programming methodologies which however impedes their wider adoption in suitable applications domains, including SDR DSP. In an effort to address this, a plethora of different high-level tool-flows have been developed. Several comparative studies of these tool-flows have been done to help – among other benefits – designers in choosing high-level tools to use. However, there are few studies that focus on SDR DSP operations, and most existing comparative studies are not based on well-defined comparison criteria. The approach implemented in this dissertation is to use a system engineering design process, firstly, to define the qualitative comparison criteria in the form of a specification for an ideal high-level SDR DSP tool-flow and, secondly, to implement a FIR filter case study in each of the tool-flows to enable a quantitative comparison in terms of programming effort and performance. The study considers Migen- and MyHDL-based open-source tool-flows for FPGA targets, and CUDA and Open Computing Language (OpenCL) for GPU targets. The ideal high-level SDR DSP tool-flow specification was defined and used to conduct a comparative study of the tools across three main design categories, which included high-level modelling, verification and implementation. For tool-flows targeting GPU platforms, the FIR case study was implemented using each of the tools; it was compiled, executed on a GPU server consisting of 2 GTX Titan-X GPUs and an Intel Core i7 GPP, and lastly profiled. The tools were moreover compared in terms of programming effort, memory transfers cost and overall operation time. With regard to tool-flows with FPGA targets, the FIR case study was developed by using each tool, and then implemented on a Xilinx 7 FPGA and compared in terms of programming effort, logic utilization and timing performance