Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

Systematic Generation of Transconductance based Variable Gain Amplifier Topologies

A systematic method for the generation of variable gain amplifier topologies is proposed. The generation is based on voltage controlled current sources (VCCSs) modelling saturated MOS transistors, resistors or combinations of these elements. It is shown that many alternative circuit topologies can be generated, that would not easily have been found in an intuitive way. Simulation results shown that significant differences in performance occur, with various mixes of specific strong and weak points. The set of alternative topologies can be used as a circuit topology database for analogue CAD system

Design of Passive Analog Electronic Circuits Using Hybrid Modified UMDA algorithm

Hybrid evolutionary passive analog circuits synthesis method based on modified Univariate Marginal Distribution Algorithm (UMDA) and a local search algorithm is proposed in the paper. The modification of the UMDA algorithm which allows to specify the maximum number of the nodes and the maximum number of the components of the synthesized circuit is proposed. The proposed hybrid approach efficiently reduces the number of the objective function evaluations. The modified UMDA algorithm is used for synthesis of the topology and the local search algorithm is used for determination of the parameters of the components of the designed circuit. As an example the proposed method is applied to a problem of synthesis of the fractional capacitor circuit

Chaos From Switched-Capacitor Circuits: Discrete Maps

A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation phenomena in nonlinear discrete dynamical systems modeled by discrete maps *n + t = fan)-Experimental results are given for four switched-capacitor circuits described by well-known discrete maps; namely, the logistic map, the piecewise-linear unimodal (one-hump) map, the H é non map, and the Lozi map

Optimizing construction of scheduled data flow graph for on-line testability

The objective of this work is to develop a new methodology for behavioural synthesis using a flow of synthesis, better suited to the scheduling of independent calculations and non-concurrent online testing. The traditional behavioural synthesis process can be defined as the compilation of an algorithmic specification into an architecture composed of a data path and a controller. This stream of synthesis generally involves scheduling, resource allocation, generation of the data path and controller synthesis. Experiments showed that optimization started at the high level synthesis improves the performance of the result, yet the current tools do not offer synthesis optimizations that from the RTL level. This justifies the development of an optimization methodology which takes effect from the behavioural specification and accompanying the synthesis process in its various stages. In this paper we propose the use of algebraic properties (commutativity, associativity and distributivity) to transform readable mathematical formulas of algorithmic specifications into mathematical formulas evaluated efficiently. This will effectively reduce the execution time of scheduling calculations and increase the possibilities of testability

Evolutionary Synthesis of Fractional Capacitor Using Simulated Annealing Method

Synthesis of fractional capacitor using classical analog circuit synthesis method was described in [6]. The work presented in this paper is focused on synthesis of the same problem by means of evolutionary method simulated annealing. Based on given desired characteristic function as input impedance or transfer function, the proposed method is able to synthesize topology and values of the components of the desired analog circuit. Comparison of the results given in [6] and results obtained by the proposed method will be given and discussed

Generalized Coupled-line All-Pass Phasers

Generalized coupled-line all-pass phasers, based on transversally-cascaded (TC), longitudinally-cascaded (LC) and hybrid-cascaded (HC) coupled transmission line sections, are presented and demonstrated using analytical, full-wave and experimental results. It is shown that for N commensurate coupled-line sections, LC and TC phasers exhibit N group delay peaks per coupled-line section harmonic frequency band, in contrast to the TC configuration, which exhibits only one peak within this band. It is also shown that for a given maximum achievable coupling-coefficient, the HC configuration provides the largest group delay swing. A wave-interference analysis is finally applied to the various coupled-line phasers, explaining their unique group delay characteristics based on physical wave-propagation mechanisms.Comment: 10 pages, 11 figure