Energy-efficient traffic engineering

The energy consumption in telecommunication networks is expected to grow considerably, especially in core networks. In this chapter, optimization of energy consumption is approached from two directions. In a first study, multilayer traffic engineering (MLTE) is used to assign energy-efficient paths and logical topology to IP traffic. The relation with traditional capacity optimization is explained, and the MLTE strategy is applied for daily traffic variations. A second study considers the core network below the IP layer, giving a detailed power consumption model. Optical bypass is evaluated as a technique to achieve considerable power savings over per-hop opticalelectronicoptical regeneration. Document type: Part of book or chapter of boo

Time-Reversal Routing for Dispersion Code Multiple Access (DCMA) Communications

We present the modeling and characterization of a time-reversal routing dispersion code multiple access (TR-DCMA) system. We show that this system maintains the low complexity advantage of DCMA transceivers while offering dynamic adaptivity for practial communication scenarios. We first derive the mathematical model and explain operation principles of the system, and then characterize its interference, signal to interference ratio, and bit error probability characteristics

An analytical performance model for the Spidergon NoC

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator