Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations

Large-scale (or massive) multiple-input multiple-output (MIMO) is expected to be one of the key technologies in next-generation multi-user cellular systems, based on the upcoming 3GPP LTE Release 12 standard, for example. In this work, we propose - to the best of our knowledge - the first VLSI design enabling high-throughput data detection in single-carrier frequency-division multiple access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate matrix inversion algorithm relying on a Neumann series expansion, which substantially reduces the complexity of linear data detection. We analyze the associated error, and we compare its performance and complexity to those of an exact linear detector. We present corresponding VLSI architectures, which perform exact and approximate soft-output detection for large-scale MIMO systems with various antenna/user configurations. Reference implementation results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale MIMO system. We finally provide a performance/complexity trade-off comparison using the presented FPGA designs, which reveals that the detector circuit of choice is determined by the ratio between BS antennas and users, as well as the desired error-rate performance.Comment: To appear in the IEEE Journal of Selected Topics in Signal Processin

Micro/Nano Manufacturing

Micro manufacturing involves dealing with the fabrication of structures in the size range of 0.1 to 1000 µm. The scope of nano manufacturing extends the size range of manufactured features to even smaller length scales—below 100 nm. A strict borderline between micro and nano manufacturing can hardly be drawn, such that both domains are treated as complementary and mutually beneficial within a closely interconnected scientific community. Both micro and nano manufacturing can be considered as important enablers for high-end products. This Special Issue of Applied Sciences is dedicated to recent advances in research and development within the field of micro and nano manufacturing. The included papers report recent findings and advances in manufacturing technologies for producing products with micro and nano scale features and structures as well as applications underpinned by the advances in these technologies

Cooperative Partial Detection for MIMO Relay Networks

This paper was submitted by the author prior to final official version. For official version please see http://hdl.handle.net/1911/64372Cooperative communication has recently re-emerged as a possible paradigm shift to realize the promises of the ever increasing wireless communication market; how- ever, there have been few, if any, studies to translate theoretical results into feasi- ble schemes with their particular practical challenges. The multiple-input multiple- output (MIMO) technique is another method that has been recently employed in different standards and protocols, often as an optional scenario, to further improve the reliability and data rate of different wireless communication applications. In this work, we look into possible methods and algorithms for combining these two tech- niques to take advantage of the benefits of both. In this thesis, we will consider methods that consider the limitations of practical solutions, which, to the best of our knowledge, are the first time to be considered in this context. We will present complexity reduction techniques for MIMO systems in cooperative systems. Furthermore, we will present architectures for flexible and configurable MIMO detectors. These architectures could support a range of data rates, modulation orders and numbers of antennas, and therefore, are crucial in the different nodes of cooperative systems. The breadth-first search employed in our realization presents a large opportunity to exploit the parallelism of the FPGA in order to achieve high data rates. Algorithmic modifications to address potential sequential bottlenecks in the traditional bread-first search-based SD are highlighted in the thesis. We will present a novel Cooperative Partial Detection (CPD) approach in MIMO relay channels, where instead of applying the conventional full detection in the relay, the relay performs a partial detection and forwards the detected parts of the message to the destination. We will demonstrate how this approach leads to controlling the complexity in the relay and helping it choose how much it is willing to cooperate based on its available resources. We will discuss the complexity implications of this method, and more importantly, present hardware verification and over-the-air experimentation of CPD using the Wireless Open-access Research Platform (WARP).NSF grants EIA-0321266, CCF-0541363, CNS-0551692, CNS-0619767, EECS-0925942, and CNS-0923479, Nokia, Xilinx, Nokia Siemens Networks, Texas Instruments, and Azimuth Systems

Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks

CYCLOSTATIONARY FEATURES BASED LOW COMPLEXITY MUTLIRESOLUTION SPECTRUM SENSING FOR COGNITVE RADIO APPLICATIONS

The demand for variety of services using wireless communication has grown remarkably in the past few many years, consequently causing an acute problem of spectrum scarcity. Today, it is one of the most challenging problems in modern wireless communication. To overcome this, the concept of cognitive radio has been proposed and this technology is fast maturing. The first and foremost function a cognitive radio must do is to sense the spectrum as accurately as possible and do it with least complexity. Among many techniques of spectrum sensing, the Multi-resolution Spectrum Sensing (MRSS) is a popular technique in recent literature. Various multi resolution techniques are used that include wavelet based spectrum estimation and spectral hole detection, wavelet based multi-resolution in analog domain and multi-resolution multiple antenna based detection. However, the basic idea is the same - the total bandwidth is sensed using coarse resolution energy detection, then, fine sensing is applied to the portion of interest. None of these techniques, however, use multi-resolution sensing using cyclostationary features for cognitive radio applications which are more reliable but computationally expensive. In this thesis, we suggest a cyclostationary features based low complexity multi-resolution spectrum sensing for cognitive radio applications. The proposed technique discussed in this thesis is inspired by the quickness of multi-resolution and the reliability of cyclostationary feature detection. The performance of the proposed scheme is primarily evaluated by its complexity analysis and by determining the minimum signal-to-noise ratio that gives 90% probability of correct classification. Both subjective and objective evaluation show that the proposed scheme is not only superior to the commonly used energy detection method but also to various multi-resolution sensing techniques as it relies on the robustness of cyclostationary feature detection. The results found are encouraging and the proposed algorithms are proved to be not only fast but also more robust and reliable

A hardware abstraction layer for the MicroTCA-based Global Trigger for the CMS experiment at CERN

Der Large Hadron Collider (LHC) am CERN bei Genf produziert mit einer Frequenz von 40 MHz Teilchenkollisionen. Jede dieser Kollisionen benötigt nachdem sie vom CMS Detektor aufgezeichnet worden ist etwa 1 MB an Speicher. Um diese enorme Menge an Daten zu reduzieren wurde ein komplexes Filter-System entwickelt. Die erste Stufe dieses Systems nimmt der Level-1 Trigger ein, der die Rate an aufgezeichneten Kollisionen auf 100 kHz reduziert. Diese Kollisionen können anschließend von einer großen Rechenfarm analysiert und weiter gefiltert werden. Der LHC wird in absehbarer Zukunft ausgebaut werden um Kollisionen mit noch mehr beteiligten Teilchen zu produzieren, was eine Verbesserung des Level-1 Triggers notwendig macht. Diese Arbeit beschäftigt sich mit den Plänen zu diesem Ausbau innerhalb des Global Trigger (GT) Projekts und führte schlussendlich zur Entwicklung einer hardware abstraction layer (HAL), die entfernten Zugriff auf Hardware-Register über Ethernet erlaubt wie auch abstrakte Elemente zur Verfügung stellt um die Information in den Registern zu repräsentieren. Abschließend wird eine Studie über die Effizienz des Global Muon Trigger präsentiert die zu Verbesserungen für die Datennahme ab dem Jahr 2011 geführt hat.The Large Hadron Collider (LHC) based at CERN near Geneva collides proton bunches at a rate of 40 MHz. Each collision produces approximately 1 MB of data in the Compact Muon Solenoid (CMS) detector. In order to reduce this event rate to a more manageable amount, a complex filter system was developed. The first stage of this filter is the so-called Level-1 trigger. This system reduces the incoming event rate to 100 kHz which can then be analyzed and filtered further in a massive computing farm. The LHC is scheduled to be upgraded to provide collisions with even more particles involved thus making an upgrade of the Level-1 trigger necessary. This thesis is concerned with the upgrade plans of the GlobalTrigger (GT) project and ultimately lead to the development ofa hardware abstraction layer (HAL) which can provide remote register-level access via Ethernet as well as abstract items to represent the information stored in the registers. Finally a study of the Global Muon Trigger (GMT) efficiency is presented

CYCLOSTATIONARY FEATURES BASED LOW COMPLEXITY MUTLIRESOLUTION SPECTRUM SENSING FOR COGNITVE RADIO APPLICATIONS

The demand for variety of services using wireless communication has grown remarkably in the past few many years, consequently causing an acute problem of spectrum scarcity. Today, it is one of the most challenging problems in modern wireless communication. To overcome this, the concept of cognitive radio has been proposed and this technology is fast maturing. The first and foremost function a cognitive radio must do is to sense the spectrum as accurately as possible and do it with least complexity. Among many techniques of spectrum sensing, the Multi-resolution Spectrum Sensing (MRSS) is a popular technique in recent literature. Various multi resolution techniques are used that include wavelet based spectrum estimation and spectral hole detection, wavelet based multi-resolution in analog domain and multi-resolution multiple antenna based detection. However, the basic idea is the same - the total bandwidth is sensed using coarse resolution energy detection, then, fine sensing is applied to the portion of interest. None of these techniques, however, use multi-resolution sensing using cyclostationary features for cognitive radio applications which are more reliable but computationally expensive. In this thesis, we suggest a cyclostationary features based low complexity multi-resolution spectrum sensing for cognitive radio applications. The proposed technique discussed in this thesis is inspired by the quickness of multi-resolution and the reliability of cyclostationary feature detection. The performance of the proposed scheme is primarily evaluated by its complexity analysis and by determining the minimum signal-to-noise ratio that gives 90% probability of correct classification. Both subjective and objective evaluation show that the proposed scheme is not only superior to the commonly used energy detection method but also to various multi-resolution sensing techniques as it relies on the robustness of cyclostationary feature detection. The results found are encouraging and the proposed algorithms are proved to be not only fast but also more robust and reliable

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures