A Switch Architecture for Real-Time Multimedia Communications

In this paper we present a switch that can be used to transfer multimedia type of trafJic. The switch provides a guaranteed throughput and a bounded latency. We focus on the design of a prototype Switching Element using the new technology opportunities being offered today. The architecture meets the multimedia requirements but still has a low complexity and needs a minimum amount of hardware. A main item of this paper will be the background of the architectural design decisions made. These include the interconnection topology, buffer organization, routing and scheduling. The implementation of the switching fabric with FPGAs, allows us to experiment with switching mode, routing strategy and scheduling policy in a multimedia environment. The witching elements are interconnected in a Kautz topology. Kautz graphs have interesting properties such as: a small diametec the degree is independent of the network size, the network is fault-tolerant and has a simple routing algorithm

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Modeling and Analysis of Fault Tolerant Multistage Interconnection Networks

Performance and reliability are two of the most crucial issues in today\u27s high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

Virtual lines, a deadlock-free and real-time routing mechanism for ATM networks

In this paper, we present a routing mechanism and buffer allocation mechanism for an ATM switching fabric. Since the fabric will be used to transfer multimedia traffic, it should provide a guaranteed throughput and a bounded latency. We focus on the design of a suitable routing mechanism that is capable of fulfilling these requirements and is free of deadlocks. We will describe two basic concepts that can be used to implement deadlock-free routing. Routing of messages is closely related to buffering. We have organized the buffers into parallel FIFO's, each representing a virtual line. In this way, we not only have solved the problem of head of line blocking, but we can also give real-time guarantees. We will show that for local high-speed networks, it is more advantageous to have a proper flow control than to have large buffers. Although the virtual line concept can have a low buffer utilization, the transfer efficiency can be higher. The virtual line concept allows adaptive routing. The total throughput of the network can be improved by using alternative routes. Adaptive routing is attractive in networks where alternative routes are not much longer than the initial route(s). The network of the switching fabric is built up from switching elements interconnected in a Kautz topology

A Bypass-Ring Scheme for a Fault Tolerant Multicast

We present a fault tolerant scheme for recovery from single or multiple node failures in multi-directional multicast trees. The scheme is based on cyclic structures providing alternative paths to eliminate faulty nodes and reroute the traffic. Our scheme is independent of message source and direction in the tree, provides a basis for on-the-fly repair and can be used as a platform for various strategies for reconnecting tree partitions. It only requires an underlying infrastructure to provide a reliable routing service. Although it is described in the context of a message multicast, the scheme can be used universally in all systems using tree-based overlay networks for communication among components

Design and implementation of high speed multimedia network.

by Yeung Chung Toa.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 63-[65]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Bandwidth required by multimedia applications --- p.1Chapter 1.2 --- Real-time requirement --- p.2Chapter 1.3 --- Multicasting --- p.2Chapter 1.4 --- Other networks --- p.3Chapter 1.5 --- Overview of CUM LAUDE NET --- p.5Chapter 1.5.1 --- Protocols --- p.7Chapter 1.5.2 --- Network Services --- p.8Chapter 1.6 --- Scope of the Thesis --- p.9Chapter 2 --- Network Architecture --- p.11Chapter 2.1 --- CUM LAUDE NET Architectural Overview --- p.11Chapter 2.2 --- Level One Network Architecture --- p.12Chapter 2.3 --- Level-One Router --- p.14Chapter 2.3.1 --- packet forwarding --- p.14Chapter 2.3.2 --- packet insertion --- p.15Chapter 2.3.3 --- packet removal --- p.15Chapter 2.3.4 --- fault protection --- p.15Chapter 2.4 --- Hub --- p.16Chapter 2.5 --- Host & Network Interface Card --- p.17Chapter 3 --- Protocol --- p.19Chapter 3.1 --- Design Overview --- p.19Chapter 3.2 --- Layering --- p.20Chapter 3.3 --- "Segment, Datagram, and Packet Format" --- p.21Chapter 3.3.1 --- IP/VCI field --- p.23Chapter 3.4 --- Data Link --- p.23Chapter 3.4.1 --- byte format and data link synchronization --- p.23Chapter 3.4.2 --- access control byte --- p.24Chapter 3.4.3 --- packet/frame boundary --- p.26Chapter 3.5 --- Fast Packet Routing Protocol --- p.26Chapter 3.5.1 --- Level-2/Level-l Bridge/Router --- p.27Chapter 3.5.2 --- Level-1 Hub --- p.29Chapter 3.5.3 --- Local Host NIC --- p.29Chapter 3.6 --- Media Access Control Protocol I : ACTA --- p.30Chapter 3.7 --- Media Access Control Protocol II: Hub Polling --- p.34Chapter 3.8 --- Protocol Implementation on CUM LAUDE NET --- p.36Chapter 4 --- Hardware Implementation & Performance of Routers and NIC --- p.40Chapter 4.1 --- Functionality of Router --- p.40Chapter 4.2 --- Important Components Used in the Router Design --- p.43Chapter 4.2.1 --- TAXI Transmitter and Receiver --- p.43Chapter 4.2.2 --- First-In-First-Out Memory (FIFO) --- p.44Chapter 4.3 --- Design of Router --- p.45Chapter 4.3.1 --- Version 1 --- p.45Chapter 4.3.2 --- Version 2 --- p.47Chapter 4.3.3 --- Version 3 --- p.50Chapter 4.4 --- Lessons Learned from the High Speed Router Design --- p.57Chapter 5 --- Conclusion --- p.61Bibliography --- p.6

Virtual lines, a deadlock free and real-time routing mechanism for ATM networks

In this paper we present a routing mechanism and buffer allocation mechanism for an ATM switching fabric. Since the fabric will be used to transfer multimedia traffic it should provide a guaranteed throughput and a bounded latency. We focus on the design of a suitable routing mechanism that is capable to fulfil these requirements and is free of deadlocks. We will describe two basic concepts that can be used to implement deadlock free routing. Routing of messages is closely related to buffering. We have organized the buffers into parallel fifos, each representing a virtual line. In this way we not only have solved the problem of Head Of Line blocking, but we can also give real-time guarantees. We will show that for local high-speed networks it is more advantageous to have a proper flow control than to have large buffers. Although the virtual line concept can have a low buffer utilization, the transfer efficiency can be higher. The virtual lines concept allows adaptive routing. The total throughput of the network can be improved by using alternative routes. Adaptive routing is attractive in networks where alternative routes are not much longer than the initial route(s). The network of the switching fabric is built up from switching elements interconnected in a Kautz topology