6 research outputs found
Minimization of NBTI performance degradation using internal node control
Abstract—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units because these units can be subjected to static NBTI stress for extended periods of time. This paper proposes internal node control, in which the inputs to individual gates are directly manipulated to prevent this static NBTI fatigue. We give a mixed integer linear program formulation for an optimal solution to this problem. The optimal placement of internal node control yields an average 26.7 % reduction in NBTI-induced delay over a ten year period for the ISCAS85 benchmarks. We find that the problem is NP-complete and present a linear-time heuristic that can be used to quickly find near-optimal solutions. The heuristic solutions are, on average, within 0.17 % of optimal and all were within 0.60% of optimal. I
Resilient Design for Process and Runtime Variations
The main objective of this thesis is to tackle the impact of parameter variations in order to improve the chip performance and extend its lifetime
Minimizing and exploiting leakage in VLSI
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at
an alarmingly rapid rate. This increase in power consumption, coupled with the increasing
demand for portable/hand-held electronics, has made power consumption a dominant
concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has
dominated the total power consumption of VLSI circuits. However, due to process scaling
trends, leakage power has now become a major component of the total power consumption
in VLSI circuits. This dissertation explores techniques to reduce leakage, as well as
techniques to exploit leakage currents through the use of sub-threshold circuits.
This dissertation consists of two studies. In the first study, techniques to reduce leakage
are presented. These include a low leakage ASIC design methodology that uses high
VT sleep transistors selectively, a methodology that combines input vector control and circuit
modification, and a scheme to find the optimum reverse body bias voltage to minimize
leakage.
As the minimum feature size of VLSI fabrication processes continues to shrink with
each successive process generation (along with the value of supply voltage and therefore the
threshold voltage of the devices), leakage currents increase exponentially. Leakage currents
are hence seen as a necessary evil in traditional VLSI design methodologies. We present
an approach to turn this problem into an opportunity. In the second study in this dissertation,
we attempt to exploit leakage currents to perform computation. We use sub-threshold
digital circuits and come up with ways to get around some of the pitfalls associated with sub-threshold circuit design. These include a technique that uses body biasing adaptively
to compensate for Process, Voltage and Temperature (PVT) variations, a design approach
that uses asynchronous micro-pipelined Network of Programmable Logic Arrays (NPLAs)
to help improve the throughput of sub-threshold designs, and a method to find the optimum
supply voltage that minimizes energy consumption in a circuit