6 research outputs found
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
DAMO: Deep Agile Mask Optimization for Full Chip Scale
Continuous scaling of the VLSI system leaves a great challenge on
manufacturing and optical proximity correction (OPC) is widely applied in
conventional design flow for manufacturability optimization. Traditional
techniques conducted OPC by leveraging a lithography model and suffered from
prohibitive computational overhead, and mostly focused on optimizing a single
clip without addressing how to tackle the full chip. In this paper, we present
DAMO, a high performance and scalable deep learning-enabled OPC system for full
chip scale. It is an end-to-end mask optimization paradigm which contains a
Deep Lithography Simulator (DLS) for lithography modeling and a Deep Mask
Generator (DMG) for mask pattern generation. Moreover, a novel layout splitting
algorithm customized for DAMO is proposed to handle the full chip OPC problem.
Extensive experiments show that DAMO outperforms the state-of-the-art OPC
solutions in both academia and industrial commercial toolkit
Journal of Microelectronic Research - May 2003
https://scholarworks.rit.edu/meec_archive/1012/thumbnail.jp