Un nuevo Código de Corrección de Errores matricial con baja redundancia

Actualmente, y debido al continuo aumento en la escala de integración, la tasa de fallos en los sistemas de memoria de los computadores ha aumentado. Así, la probabilidad de que se produzcan Single Cell Upsets (SCUs) o Multiple Cell Upsets (MCUs) aumenta. Una solución común es el uso de Códigos de Corrección de Errores (ECCs). Sin embargo, cuando se utilizan ECCs en aplicaciones empotradas, se debe lograr un buen equilibrio entre la cobertura de errores, la redundancia introducida y la eficiencia en términos de área de silicio ocupada, potencia consumida y retardo de los circuitos de codificación y decodificación. En este sentido, existen diferentes propuestas para tolerar MCUs. Por ejemplo, los códigos matriciales utilizan códigos de Hamming y controles de paridad en un formato bidimensional para detectar y/o corregir MCUs. Sin embargo, estos códigos introducen una gran redundancia, lo que conlleva una sobrecarga excesiva con respecto al área, potencia consumida y retardo. En este trabajo presentamos un nuevo código matricial con una baja redundancia, que permite corregir diferentes patrones de MCUs y que no introduce una gran sobrecarga en los circuitos de codificación y decodificación

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

© 2018 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column¿line¿code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new lowredundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes.This work was supported by the Spanish Government under the research Project TIN2016-81075-R.Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(10):2132-2142. https://doi.org/10.1109/TVLSI.2018.2837220S21322142261

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

[EN] The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.© 2021 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Gracia-Morán, J.; Saiz-Adalid, L.; Baraza-Calvo, J.; Gil Tomás, DA.; Gil, P. (2021). Design, Implementation and Evaluation of a Low Redundant Error Correction Code. IEEE Latin America Transactions. 19(11):1903-1911. https://doi.org/10.1109/TLA.2021.947562419031911191