Conception et mise au point de l'électronique frontale du détecteur de pied de gerbe (Preshower) de l'expérience CMS

Modern particle physics collider experiments consist of a number of macroscopic modules each consisting of large number of sensors measuring charge deposition from traversing particles. The CMS Preshower detector is designed as a sampling calorimeter producing electromagnetic showers for incident electrons and photons resulting from LHC p-p interactions. The ultimate aim is to provide neutral pion / gamma separation reducing the background to the most promising Higgs channel, SM Higgs to 2 photons. The detector has 4300 silicon sensors each subdivided into 32 channels with a total sensitive area of 16.4 m2. Front-end microelectronics ASICs must measure the charge of each channel accurately with low noise and over a wide dynamic range (4 fC to 1600 fC) at the rate of 40 MHz within a harsh radiation environment. This thesis presents the design and development of the Preshower front-end electronics ASIC development, PACE. The first chapter introduces the Preshower experiment and defines the specification for PACE as derived from the physics. The second chapter examines the radiation environment, its effect on electronic devices, and design techniques / technologies that can resist to LHC radiation levels. Chapters 3 to 5 present the design and results of two PACE developments examining analog memories based on current and voltage sampling techniques. Experimental results from a Preshower electro-mechanical prototype tested in a particle beam are also given

An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

DEVELOPMENT OF AN UWB RADAR SYSTEM

An ultra-wideband radar system is built at the University of Tennessee with the goal to develop a ground penetrating radar (GPR). The radar is required to transmit and receive a very narrow pulse signal in the time domain. The bistatic radar transmits a pulse through an ultrawide spiral antenna and receives the pulse by a similar antenna. Direct sampling is used to improve the performance of the impulse radar allowing up to 1.5 GHz of bandwidth to be used for signal processing and target detection with high resolution. Using direct sampling offers a less complex system design than traditional lower sample rate, super-heterodyne systems using continuous wave or step frequency methods while offering faster results than conventional equivalent time sampling techniques that require multiple data sets and significant post-processing. These two points are particularly important for a system that may be used in the field in potentially dangerous environments. Direct sampling radar systems, while still frequency limited, are continually improving their upper frequencies boundaries due to more power efficient, higher sampling rate analog to digital converters (ADCs) which relates directly to better subsurface resolution for potential target detection

Ultra-Wideband CMOS Transceiver Front-End for Bio-Medical Radar Sensing

Since the Federal Communication Commission released the unlicensed 3.1-10.6 GHz frequency band for commercial use in early 2002, the ultra wideband (UWB) has developed from an emerging technology into a mainstream research area. The UWB technology, which utilizes wide spectrum, opens a new era of possibility for practical applications in radar sensing, one of which is the human vital sign monitoring. The aim of this thesis is to study and research the possibility of a new generation humanrespiration monitoring sensor using UWB radar technology and to develop a new prototype of UWB radar sensor for system-on-chip solutions in CMOS technology. In this thesis, a lowpower Gaussian impulse UWB mono-static radar transceiver architecture is presented. The UWB Gaussian pulse transmitter and receiver are implemented and fabricated using 90nm CMOS technology. Since the energy of low order Gaussian pulse is mostly condensed at lower frequency, in order to transmit the pulse in a very efficient way, higher order Gaussian derivative pulses are desired as the baseband signal. This motivates the advancement of the design into UWB high-order pulse transmitter. Both the Gaussian impulse UWB transmitter and Gaussian higher-order impulse UWB transmitter take the low-power and high-speed advantage of digital circuit to generate different waveforms. The measurement results are analyzed and discussed. This thesis also presents a low-power UWB mono-static radar transceiver architecture exploiting the full benefit of UWB bandwidth in radar sensing applications. The transceiver includes a full UWB band transmitter, an UWB receiver front-end, and an on-chip diplexer. The non-coherent UWB transmitter generates pulse modulated baseband signals at different carrier frequencies within the designated 3-10 GHz band using a digitally controlled pulse generator. The test shows the proposed radar transceiver can detect the human respiration pattern within 50 cm distance. The applications of this UWB radar sensing solution in commercialized standard CMOS technology include constant breathing pattern monitoring for gated radiation therapy, realtime monitoring of patients, and any other breathing monitoring. The research paves the way to wireless technology integration with health care and bio-sensor network

Development of radiation hard readout electronics for LHCb

Das Experiment LHCB am CERN ist zur Zeit in der Entwicklungsphase und hat zum Ziel, CP-Verletzung im System der B-Mesonen mit sehr hoher Präzision zu messen. In dem Experiment wird ein mit Silizium-Mikrostreifenzähler n ausgestatteter Vertex-Detektor eingesetzt. Ein Mikrochip, der für die Auslese dieser Detektorkomponente geignet ist, wurde in einer Arbeitsgruppe im ASIC-Labor Heidelberg entwickelt. Dieser Auslesechip Beetle-1.0 besteht aus 128 analogen Eingangsstufen mit einem ladungsempfindlichen Vorverstärker, einem Pulsformer und einer Treiberstufe. Das analoge Signal wird auf einen Komparator geführt, von dem ein schnelles Triggersignal abgeleitet werden kann. Der darauf folgende Ringspeicher (aufgebaut als Matrix von Gate-Kapazitäten) kann entweder zur Speicherung des analogen Signals der Eingangsstufe oder zur Speicherung des digitalen Ausgangs des Komparators benutzt werden. Ein externes Triggersignal markiert Ereignisse, die ausgelesen werden sollen, wobei die zugehörige Stelle in dem Ringspeicher in einem Derandomizer abgelegt wird. Markierte Ereignisse werden mittels einem rücksetzbaren ladungsempfindlichen Verstärker ausgelesen. Ein analoger Multiplexer, der die Signale abhängig vom Aulesemodus im Verhältniss 32:1, 64:1 oder 128:1 seriell weitergibt, schliest sich daran an. Durch einen Stromtreiber werden die Daten von dem dem Chip ausgegeben. Beim Einsatz des Beetle im Vertexdetektor von LHCb muss er einer Strahlendosis von insgesamt 10 MRad standhalten. Dies wurde durch den Einsatz einer CMOS-Technology mit Strukturbreiten von 0,25um sowie geschlossener Geometrie von nMOS-Transistoren erreicht. Im Rahmen dieser Doktorarbeit wurden wesentliche Komponenten der analogen Auslesekette des Beetle-1.0 entworfen und getestet. Dazu wurde auf Ergebnisse von intensiven Messungen an dem Auslesechip HELIX128 zurückgegriffen. Ebenso wurden Teile des SCTA Auslesechips modifiziert, um diesen für das Experiment LHCb einsetzen zu können