The operational characteristics and potential applications of a low voltage EMCCD in a CMOS process

The Electron Multiplying Test Chip 1 (EMTC1) was developed with the aim of creating a device which could produce superior Electron Multiplication (EM) gain at a greatly reduced voltage. An EM gain exceeding 3% per stage has been recorded for a relatively low voltage (~13.0V) from two recently developed pixel structures. An electro-optical characterisation of the EMTC1 is presented focusing on charge transfer via experimental and simulation results aiming to provide insight into the transfer and multiplication process. The Charge Transfer Inefficiency (CTI) is analysed with the aim of providing a greater understanding of the charge transfer process. Light starved applications such as Earth observation and automated inspection are known to benefit from Time Delay Integration (TDI) and electron multiplication. Though traditionally implemented in CCDs, implementing TDI in CMOS technology can lead to an increase of functionality, higher readout speeds and reduced noise. This paper presents a discussion of the implication of these results on the potential applications of this sensor

Electron Multiplying Low-Voltage CCD With Increased Gain

Novel designs for the gain elements in electron multiplying (EM) CCDs have been implemented in a device manufactured in a low voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this work can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain ageing