47 research outputs found
A technology based complexity model for reversible Cuccaro ripple-carry adder
Reversible logic provides an alternative to classical computing, that may overcome many of the power dissipation problems. The paper presents a simple complexity model, from the study of a cascade of Cuccaro adders processed in standard 0.35 micrometer CMOS technology
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
On the Effect of Quantum Interaction Distance on Quantum Addition Circuits
We investigate the theoretical limits of the effect of the quantum
interaction distance on the speed of exact quantum addition circuits. For this
study, we exploit graph embedding for quantum circuit analysis. We study a
logical mapping of qubits and gates of any -depth quantum adder
circuit for two -qubit registers onto a practical architecture, which limits
interaction distance to the nearest neighbors only and supports only one- and
two-qubit logical gates. Unfortunately, on the chosen -dimensional practical
architecture, we prove that the depth lower bound of any exact quantum addition
circuits is no longer , but . This
result, the first application of graph embedding to quantum circuits and
devices, provides a new tool for compiler development, emphasizes the impact of
quantum computer architecture on performance, and acts as a cautionary note
when evaluating the time performance of quantum algorithms.Comment: accepted for ACM Journal on Emerging Technologies in Computing
System
Time-Sliced Quantum Circuit Partitioning for Modular Architectures
Current quantum computer designs will not scale. To scale beyond small
prototypes, quantum architectures will likely adopt a modular approach with
clusters of tightly connected quantum bits and sparser connections between
clusters. We exploit this clustering and the statically-known control flow of
quantum programs to create tractable partitioning heuristics which map quantum
circuits to modular physical machines one time slice at a time. Specifically,
we create optimized mappings for each time slice, accounting for the cost to
move data from the previous time slice and using a tunable lookahead scheme to
reduce the cost to move to future time slices. We compare our approach to a
traditional statically-mapped, owner-computes model. Our results show strict
improvement over the static mapping baseline. We reduce the non-local
communication overhead by 89.8\% in the best case and by 60.9\% on average. Our
techniques, unlike many exact solver methods, are computationally tractable.Comment: Appears in CF'20: ACM International Conference on Computing Frontier